git.sur5r.net Git - u-boot/blob - drivers/ddr/fsl/ctrl_regs.c

   1 /*
   2  * Copyright 2008-2016 Freescale Semiconductor, Inc.
   3  * Copyright 2017-2018 NXP Semiconductor
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * Generic driver for Freescale DDR/DDR2/DDR3/DDR4 memory controller.
  10  * Based on code from spd_sdram.c
  11  * Author: James Yang [at freescale.com]
  12  */
  13
  14 #include <common.h>
  15 #include <fsl_ddr_sdram.h>
  16 #include <fsl_errata.h>
  17 #include <fsl_ddr.h>
  18 #include <fsl_immap.h>
  19 #include <asm/io.h>
  20 #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) || \
  21         defined(CONFIG_ARM)
  22 #include <asm/arch/clock.h>
  23 #endif
  24
  25 /*
  26  * Determine Rtt value.
  27  *
  28  * This should likely be either board or controller specific.
  29  *
  30  * Rtt(nominal) - DDR2:
  31  *      0 = Rtt disabled
  32  *      1 = 75 ohm
  33  *      2 = 150 ohm
  34  *      3 = 50 ohm
  35  * Rtt(nominal) - DDR3:
  36  *      0 = Rtt disabled
  37  *      1 = 60 ohm
  38  *      2 = 120 ohm
  39  *      3 = 40 ohm
  40  *      4 = 20 ohm
  41  *      5 = 30 ohm
  42  *
  43  * FIXME: Apparently 8641 needs a value of 2
  44  * FIXME: Old code seys if 667 MHz or higher, use 3 on 8572
  45  *
  46  * FIXME: There was some effort down this line earlier:
  47  *
  48  *      unsigned int i;
  49  *      for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL/2; i++) {
  50  *              if (popts->dimmslot[i].num_valid_cs
  51  *                  && (popts->cs_local_opts[2*i].odt_rd_cfg
  52  *                      || popts->cs_local_opts[2*i].odt_wr_cfg)) {
  53  *                      rtt = 2;
  54  *                      break;
  55  *              }
  56  *      }
  57  */
  58 static inline int fsl_ddr_get_rtt(void)
  59 {
  60         int rtt;
  61
  62 #if defined(CONFIG_SYS_FSL_DDR1)
  63         rtt = 0;
  64 #elif defined(CONFIG_SYS_FSL_DDR2)
  65         rtt = 3;
  66 #else
  67         rtt = 0;
  68 #endif
  69
  70         return rtt;
  71 }
  72
  73 #ifdef CONFIG_SYS_FSL_DDR4
  74 /*
  75  * compute CAS write latency according to DDR4 spec
  76  * CWL = 9 for <= 1600MT/s
  77  *       10 for <= 1866MT/s
  78  *       11 for <= 2133MT/s
  79  *       12 for <= 2400MT/s
  80  *       14 for <= 2667MT/s
  81  *       16 for <= 2933MT/s
  82  *       18 for higher
  83  */
  84 static inline unsigned int compute_cas_write_latency(
  85                                 const unsigned int ctrl_num)
  86 {
  87         unsigned int cwl;
  88         const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
  89         if (mclk_ps >= 1250)
  90                 cwl = 9;
  91         else if (mclk_ps >= 1070)
  92                 cwl = 10;
  93         else if (mclk_ps >= 935)
  94                 cwl = 11;
  95         else if (mclk_ps >= 833)
  96                 cwl = 12;
  97         else if (mclk_ps >= 750)
  98                 cwl = 14;
  99         else if (mclk_ps >= 681)
 100                 cwl = 16;
 101         else
 102                 cwl = 18;
 103
 104         return cwl;
 105 }
 106 #else
 107 /*
 108  * compute the CAS write latency according to DDR3 spec
 109  * CWL = 5 if tCK >= 2.5ns
 110  *       6 if 2.5ns > tCK >= 1.875ns
 111  *       7 if 1.875ns > tCK >= 1.5ns
 112  *       8 if 1.5ns > tCK >= 1.25ns
 113  *       9 if 1.25ns > tCK >= 1.07ns
 114  *       10 if 1.07ns > tCK >= 0.935ns
 115  *       11 if 0.935ns > tCK >= 0.833ns
 116  *       12 if 0.833ns > tCK >= 0.75ns
 117  */
 118 static inline unsigned int compute_cas_write_latency(
 119                                 const unsigned int ctrl_num)
 120 {
 121         unsigned int cwl;
 122         const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 123
 124         if (mclk_ps >= 2500)
 125                 cwl = 5;
 126         else if (mclk_ps >= 1875)
 127                 cwl = 6;
 128         else if (mclk_ps >= 1500)
 129                 cwl = 7;
 130         else if (mclk_ps >= 1250)
 131                 cwl = 8;
 132         else if (mclk_ps >= 1070)
 133                 cwl = 9;
 134         else if (mclk_ps >= 935)
 135                 cwl = 10;
 136         else if (mclk_ps >= 833)
 137                 cwl = 11;
 138         else if (mclk_ps >= 750)
 139                 cwl = 12;
 140         else {
 141                 cwl = 12;
 142                 printf("Warning: CWL is out of range\n");
 143         }
 144         return cwl;
 145 }
 146 #endif
 147
 148 /* Chip Select Configuration (CSn_CONFIG) */
 149 static void set_csn_config(int dimm_number, int i, fsl_ddr_cfg_regs_t *ddr,
 150                                const memctl_options_t *popts,
 151                                const dimm_params_t *dimm_params)
 152 {
 153         unsigned int cs_n_en = 0; /* Chip Select enable */
 154         unsigned int intlv_en = 0; /* Memory controller interleave enable */
 155         unsigned int intlv_ctl = 0; /* Interleaving control */
 156         unsigned int ap_n_en = 0; /* Chip select n auto-precharge enable */
 157         unsigned int odt_rd_cfg = 0; /* ODT for reads configuration */
 158         unsigned int odt_wr_cfg = 0; /* ODT for writes configuration */
 159         unsigned int ba_bits_cs_n = 0; /* Num of bank bits for SDRAM on CSn */
 160         unsigned int row_bits_cs_n = 0; /* Num of row bits for SDRAM on CSn */
 161         unsigned int col_bits_cs_n = 0; /* Num of ocl bits for SDRAM on CSn */
 162         int go_config = 0;
 163 #ifdef CONFIG_SYS_FSL_DDR4
 164         unsigned int bg_bits_cs_n = 0; /* Num of bank group bits */
 165 #else
 166         unsigned int n_banks_per_sdram_device;
 167 #endif
 168
 169         /* Compute CS_CONFIG only for existing ranks of each DIMM.  */
 170         switch (i) {
 171         case 0:
 172                 if (dimm_params[dimm_number].n_ranks > 0) {
 173                         go_config = 1;
 174                         /* These fields only available in CS0_CONFIG */
 175                         if (!popts->memctl_interleaving)
 176                                 break;
 177                         switch (popts->memctl_interleaving_mode) {
 178                         case FSL_DDR_256B_INTERLEAVING:
 179                         case FSL_DDR_CACHE_LINE_INTERLEAVING:
 180                         case FSL_DDR_PAGE_INTERLEAVING:
 181                         case FSL_DDR_BANK_INTERLEAVING:
 182                         case FSL_DDR_SUPERBANK_INTERLEAVING:
 183                                 intlv_en = popts->memctl_interleaving;
 184                                 intlv_ctl = popts->memctl_interleaving_mode;
 185                                 break;
 186                         default:
 187                                 break;
 188                         }
 189                 }
 190                 break;
 191         case 1:
 192                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 1) || \
 193                     (dimm_number == 1 && dimm_params[1].n_ranks > 0))
 194                         go_config = 1;
 195                 break;
 196         case 2:
 197                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 2) || \
 198                    (dimm_number >= 1 && dimm_params[dimm_number].n_ranks > 0))
 199                         go_config = 1;
 200                 break;
 201         case 3:
 202                 if ((dimm_number == 0 && dimm_params[0].n_ranks > 3) || \
 203                     (dimm_number == 1 && dimm_params[1].n_ranks > 1) || \
 204                     (dimm_number == 3 && dimm_params[3].n_ranks > 0))
 205                         go_config = 1;
 206                 break;
 207         default:
 208                 break;
 209         }
 210         if (go_config) {
 211                 cs_n_en = 1;
 212                 ap_n_en = popts->cs_local_opts[i].auto_precharge;
 213                 odt_rd_cfg = popts->cs_local_opts[i].odt_rd_cfg;
 214                 odt_wr_cfg = popts->cs_local_opts[i].odt_wr_cfg;
 215 #ifdef CONFIG_SYS_FSL_DDR4
 216                 ba_bits_cs_n = dimm_params[dimm_number].bank_addr_bits;
 217                 bg_bits_cs_n = dimm_params[dimm_number].bank_group_bits;
 218 #else
 219                 n_banks_per_sdram_device
 220                         = dimm_params[dimm_number].n_banks_per_sdram_device;
 221                 ba_bits_cs_n = __ilog2(n_banks_per_sdram_device) - 2;
 222 #endif
 223                 row_bits_cs_n = dimm_params[dimm_number].n_row_addr - 12;
 224                 col_bits_cs_n = dimm_params[dimm_number].n_col_addr - 8;
 225         }
 226         ddr->cs[i].config = (0
 227                 | ((cs_n_en & 0x1) << 31)
 228                 | ((intlv_en & 0x3) << 29)
 229                 | ((intlv_ctl & 0xf) << 24)
 230                 | ((ap_n_en & 0x1) << 23)
 231
 232                 /* XXX: some implementation only have 1 bit starting at left */
 233                 | ((odt_rd_cfg & 0x7) << 20)
 234
 235                 /* XXX: Some implementation only have 1 bit starting at left */
 236                 | ((odt_wr_cfg & 0x7) << 16)
 237
 238                 | ((ba_bits_cs_n & 0x3) << 14)
 239                 | ((row_bits_cs_n & 0x7) << 8)
 240 #ifdef CONFIG_SYS_FSL_DDR4
 241                 | ((bg_bits_cs_n & 0x3) << 4)
 242 #endif
 243                 | ((col_bits_cs_n & 0x7) << 0)
 244                 );
 245         debug("FSLDDR: cs[%d]_config = 0x%08x\n", i,ddr->cs[i].config);
 246 }
 247
 248 /* Chip Select Configuration 2 (CSn_CONFIG_2) */
 249 /* FIXME: 8572 */
 250 static void set_csn_config_2(int i, fsl_ddr_cfg_regs_t *ddr)
 251 {
 252         unsigned int pasr_cfg = 0;      /* Partial array self refresh config */
 253
 254         ddr->cs[i].config_2 = ((pasr_cfg & 7) << 24);
 255         debug("FSLDDR: cs[%d]_config_2 = 0x%08x\n", i, ddr->cs[i].config_2);
 256 }
 257
 258 /* -3E = 667 CL5, -25 = CL6 800, -25E = CL5 800 */
 259
 260 #if !defined(CONFIG_SYS_FSL_DDR1)
 261 /*
 262  * Check DIMM configuration, return 2 if quad-rank or two dual-rank
 263  * Return 1 if other two slots configuration. Return 0 if single slot.
 264  */
 265 static inline int avoid_odt_overlap(const dimm_params_t *dimm_params)
 266 {
 267 #if CONFIG_DIMM_SLOTS_PER_CTLR == 1
 268         if (dimm_params[0].n_ranks == 4)
 269                 return 2;
 270 #endif
 271
 272 #if CONFIG_DIMM_SLOTS_PER_CTLR == 2
 273         if ((dimm_params[0].n_ranks == 2) &&
 274                 (dimm_params[1].n_ranks == 2))
 275                 return 2;
 276
 277 #ifdef CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
 278         if (dimm_params[0].n_ranks == 4)
 279                 return 2;
 280 #endif
 281
 282         if ((dimm_params[0].n_ranks != 0) &&
 283             (dimm_params[2].n_ranks != 0))
 284                 return 1;
 285 #endif
 286         return 0;
 287 }
 288
 289 /*
 290  * DDR SDRAM Timing Configuration 0 (TIMING_CFG_0)
 291  *
 292  * Avoid writing for DDR I.  The new PQ38 DDR controller
 293  * dreams up non-zero default values to be backwards compatible.
 294  */
 295 static void set_timing_cfg_0(const unsigned int ctrl_num,
 296                                 fsl_ddr_cfg_regs_t *ddr,
 297                                 const memctl_options_t *popts,
 298                                 const dimm_params_t *dimm_params)
 299 {
 300         unsigned char trwt_mclk = 0;   /* Read-to-write turnaround */
 301         unsigned char twrt_mclk = 0;   /* Write-to-read turnaround */
 302         /* 7.5 ns on -3E; 0 means WL - CL + BL/2 + 1 */
 303         unsigned char trrt_mclk = 0;   /* Read-to-read turnaround */
 304         unsigned char twwt_mclk = 0;   /* Write-to-write turnaround */
 305
 306         /* Active powerdown exit timing (tXARD and tXARDS). */
 307         unsigned char act_pd_exit_mclk;
 308         /* Precharge powerdown exit timing (tXP). */
 309         unsigned char pre_pd_exit_mclk;
 310         /* ODT powerdown exit timing (tAXPD). */
 311         unsigned char taxpd_mclk = 0;
 312         /* Mode register set cycle time (tMRD). */
 313         unsigned char tmrd_mclk;
 314 #if defined(CONFIG_SYS_FSL_DDR4) || defined(CONFIG_SYS_FSL_DDR3)
 315         const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 316 #endif
 317
 318 #ifdef CONFIG_SYS_FSL_DDR4
 319         /* tXP=max(4nCK, 6ns) */
 320         int txp = max((int)mclk_ps * 4, 6000); /* unit=ps */
 321         unsigned int data_rate = get_ddr_freq(ctrl_num);
 322
 323         /* for faster clock, need more time for data setup */
 324         trwt_mclk = (data_rate/1000000 > 1900) ? 3 : 2;
 325
 326         /*
 327          * for single quad-rank DIMM and two-slot DIMMs
 328          * to avoid ODT overlap
 329          */
 330         switch (avoid_odt_overlap(dimm_params)) {
 331         case 2:
 332                 twrt_mclk = 2;
 333                 twwt_mclk = 2;
 334                 trrt_mclk = 2;
 335                 break;
 336         default:
 337                 twrt_mclk = 1;
 338                 twwt_mclk = 1;
 339                 trrt_mclk = 0;
 340                 break;
 341         }
 342
 343         act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
 344         pre_pd_exit_mclk = act_pd_exit_mclk;
 345         /*
 346          * MRS_CYC = max(tMRD, tMOD)
 347          * tMRD = 8nCK, tMOD = max(24nCK, 15ns)
 348          */
 349         tmrd_mclk = max(24U, picos_to_mclk(ctrl_num, 15000));
 350 #elif defined(CONFIG_SYS_FSL_DDR3)
 351         unsigned int data_rate = get_ddr_freq(ctrl_num);
 352         int txp;
 353         unsigned int ip_rev;
 354         int odt_overlap;
 355         /*
 356          * (tXARD and tXARDS). Empirical?
 357          * The DDR3 spec has not tXARD,
 358          * we use the tXP instead of it.
 359          * tXP=max(3nCK, 7.5ns) for DDR3-800, 1066
 360          *     max(3nCK, 6ns) for DDR3-1333, 1600, 1866, 2133
 361          * spec has not the tAXPD, we use
 362          * tAXPD=1, need design to confirm.
 363          */
 364         txp = max((int)mclk_ps * 3, (mclk_ps > 1540 ? 7500 : 6000));
 365
 366         ip_rev = fsl_ddr_get_version(ctrl_num);
 367         if (ip_rev >= 0x40700) {
 368                 /*
 369                  * MRS_CYC = max(tMRD, tMOD)
 370                  * tMRD = 4nCK (8nCK for RDIMM)
 371                  * tMOD = max(12nCK, 15ns)
 372                  */
 373                 tmrd_mclk = max((unsigned int)12,
 374                                 picos_to_mclk(ctrl_num, 15000));
 375         } else {
 376                 /*
 377                  * MRS_CYC = tMRD
 378                  * tMRD = 4nCK (8nCK for RDIMM)
 379                  */
 380                 if (popts->registered_dimm_en)
 381                         tmrd_mclk = 8;
 382                 else
 383                         tmrd_mclk = 4;
 384         }
 385
 386         /* set the turnaround time */
 387
 388         /*
 389          * for single quad-rank DIMM and two-slot DIMMs
 390          * to avoid ODT overlap
 391          */
 392         odt_overlap = avoid_odt_overlap(dimm_params);
 393         switch (odt_overlap) {
 394         case 2:
 395                 twwt_mclk = 2;
 396                 trrt_mclk = 1;
 397                 break;
 398         case 1:
 399                 twwt_mclk = 1;
 400                 trrt_mclk = 0;
 401                 break;
 402         default:
 403                 break;
 404         }
 405
 406         /* for faster clock, need more time for data setup */
 407         trwt_mclk = (data_rate/1000000 > 1800) ? 2 : 1;
 408
 409         if ((data_rate/1000000 > 1150) || (popts->memctl_interleaving))
 410                 twrt_mclk = 1;
 411
 412         if (popts->dynamic_power == 0) {        /* powerdown is not used */
 413                 act_pd_exit_mclk = 1;
 414                 pre_pd_exit_mclk = 1;
 415                 taxpd_mclk = 1;
 416         } else {
 417                 /* act_pd_exit_mclk = tXARD, see above */
 418                 act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp);
 419                 /* Mode register MR0[A12] is '1' - fast exit */
 420                 pre_pd_exit_mclk = act_pd_exit_mclk;
 421                 taxpd_mclk = 1;
 422         }
 423 #else /* CONFIG_SYS_FSL_DDR2 */
 424         /*
 425          * (tXARD and tXARDS). Empirical?
 426          * tXARD = 2 for DDR2
 427          * tXP=2
 428          * tAXPD=8
 429          */
 430         act_pd_exit_mclk = 2;
 431         pre_pd_exit_mclk = 2;
 432         taxpd_mclk = 8;
 433         tmrd_mclk = 2;
 434 #endif
 435
 436         if (popts->trwt_override)
 437                 trwt_mclk = popts->trwt;
 438
 439         ddr->timing_cfg_0 = (0
 440                 | ((trwt_mclk & 0x3) << 30)     /* RWT */
 441                 | ((twrt_mclk & 0x3) << 28)     /* WRT */
 442                 | ((trrt_mclk & 0x3) << 26)     /* RRT */
 443                 | ((twwt_mclk & 0x3) << 24)     /* WWT */
 444                 | ((act_pd_exit_mclk & 0xf) << 20)  /* ACT_PD_EXIT */
 445                 | ((pre_pd_exit_mclk & 0xF) << 16)  /* PRE_PD_EXIT */
 446                 | ((taxpd_mclk & 0xf) << 8)     /* ODT_PD_EXIT */
 447                 | ((tmrd_mclk & 0x1f) << 0)     /* MRS_CYC */
 448                 );
 449         debug("FSLDDR: timing_cfg_0 = 0x%08x\n", ddr->timing_cfg_0);
 450 }
 451 #endif  /* !defined(CONFIG_SYS_FSL_DDR1) */
 452
 453 /* DDR SDRAM Timing Configuration 3 (TIMING_CFG_3) */
 454 static void set_timing_cfg_3(const unsigned int ctrl_num,
 455                              fsl_ddr_cfg_regs_t *ddr,
 456                              const memctl_options_t *popts,
 457                              const common_timing_params_t *common_dimm,
 458                              unsigned int cas_latency,
 459                              unsigned int additive_latency)
 460 {
 461         /* Extended precharge to activate interval (tRP) */
 462         unsigned int ext_pretoact = 0;
 463         /* Extended Activate to precharge interval (tRAS) */
 464         unsigned int ext_acttopre = 0;
 465         /* Extended activate to read/write interval (tRCD) */
 466         unsigned int ext_acttorw = 0;
 467         /* Extended refresh recovery time (tRFC) */
 468         unsigned int ext_refrec;
 469         /* Extended MCAS latency from READ cmd */
 470         unsigned int ext_caslat = 0;
 471         /* Extended additive latency */
 472         unsigned int ext_add_lat = 0;
 473         /* Extended last data to precharge interval (tWR) */
 474         unsigned int ext_wrrec = 0;
 475         /* Control Adjust */
 476         unsigned int cntl_adj = 0;
 477
 478         ext_pretoact = picos_to_mclk(ctrl_num, common_dimm->trp_ps) >> 4;
 479         ext_acttopre = picos_to_mclk(ctrl_num, common_dimm->tras_ps) >> 4;
 480         ext_acttorw = picos_to_mclk(ctrl_num, common_dimm->trcd_ps) >> 4;
 481         ext_caslat = (2 * cas_latency - 1) >> 4;
 482         ext_add_lat = additive_latency >> 4;
 483 #ifdef CONFIG_SYS_FSL_DDR4
 484         ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8) >> 4;
 485 #else
 486         ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8) >> 4;
 487         /* ext_wrrec only deals with 16 clock and above, or 14 with OTF */
 488 #endif
 489         ext_wrrec = (picos_to_mclk(ctrl_num, common_dimm->twr_ps) +
 490                 (popts->otf_burst_chop_en ? 2 : 0)) >> 4;
 491
 492         ddr->timing_cfg_3 = (0
 493                 | ((ext_pretoact & 0x1) << 28)
 494                 | ((ext_acttopre & 0x3) << 24)
 495                 | ((ext_acttorw & 0x1) << 22)
 496                 | ((ext_refrec & 0x3F) << 16)
 497                 | ((ext_caslat & 0x3) << 12)
 498                 | ((ext_add_lat & 0x1) << 10)
 499                 | ((ext_wrrec & 0x1) << 8)
 500                 | ((cntl_adj & 0x7) << 0)
 501                 );
 502         debug("FSLDDR: timing_cfg_3 = 0x%08x\n", ddr->timing_cfg_3);
 503 }
 504
 505 /* DDR SDRAM Timing Configuration 1 (TIMING_CFG_1) */
 506 static void set_timing_cfg_1(const unsigned int ctrl_num,
 507                              fsl_ddr_cfg_regs_t *ddr,
 508                              const memctl_options_t *popts,
 509                              const common_timing_params_t *common_dimm,
 510                              unsigned int cas_latency)
 511 {
 512         /* Precharge-to-activate interval (tRP) */
 513         unsigned char pretoact_mclk;
 514         /* Activate to precharge interval (tRAS) */
 515         unsigned char acttopre_mclk;
 516         /*  Activate to read/write interval (tRCD) */
 517         unsigned char acttorw_mclk;
 518         /* CASLAT */
 519         unsigned char caslat_ctrl;
 520         /*  Refresh recovery time (tRFC) ; trfc_low */
 521         unsigned char refrec_ctrl;
 522         /* Last data to precharge minimum interval (tWR) */
 523         unsigned char wrrec_mclk;
 524         /* Activate-to-activate interval (tRRD) */
 525         unsigned char acttoact_mclk;
 526         /* Last write data pair to read command issue interval (tWTR) */
 527         unsigned char wrtord_mclk;
 528 #ifdef CONFIG_SYS_FSL_DDR4
 529         /* DDR4 supports 10, 12, 14, 16, 18, 20, 24 */
 530         static const u8 wrrec_table[] = {
 531                 10, 10, 10, 10, 10,
 532                 10, 10, 10, 10, 10,
 533                 12, 12, 14, 14, 16,
 534                 16, 18, 18, 20, 20,
 535                 24, 24, 24, 24};
 536 #else
 537         /* DDR_SDRAM_MODE doesn't support 9,11,13,15 */
 538         static const u8 wrrec_table[] = {
 539                 1, 2, 3, 4, 5, 6, 7, 8, 10, 10, 12, 12, 14, 14, 0, 0};
 540 #endif
 541
 542         pretoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trp_ps);
 543         acttopre_mclk = picos_to_mclk(ctrl_num, common_dimm->tras_ps);
 544         acttorw_mclk = picos_to_mclk(ctrl_num, common_dimm->trcd_ps);
 545
 546         /*
 547          * Translate CAS Latency to a DDR controller field value:
 548          *
 549          *      CAS Lat DDR I   DDR II  Ctrl
 550          *      Clocks  SPD Bit SPD Bit Value
 551          *      ------- ------- ------- -----
 552          *      1.0     0               0001
 553          *      1.5     1               0010
 554          *      2.0     2       2       0011
 555          *      2.5     3               0100
 556          *      3.0     4       3       0101
 557          *      3.5     5               0110
 558          *      4.0             4       0111
 559          *      4.5                     1000
 560          *      5.0             5       1001
 561          */
 562 #if defined(CONFIG_SYS_FSL_DDR1)
 563         caslat_ctrl = (cas_latency + 1) & 0x07;
 564 #elif defined(CONFIG_SYS_FSL_DDR2)
 565         caslat_ctrl = 2 * cas_latency - 1;
 566 #else
 567         /*
 568          * if the CAS latency more than 8 cycle,
 569          * we need set extend bit for it at
 570          * TIMING_CFG_3[EXT_CASLAT]
 571          */
 572         if (fsl_ddr_get_version(ctrl_num) <= 0x40400)
 573                 caslat_ctrl = 2 * cas_latency - 1;
 574         else
 575                 caslat_ctrl = (cas_latency - 1) << 1;
 576 #endif
 577
 578 #ifdef CONFIG_SYS_FSL_DDR4
 579         refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8;
 580         wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
 581         acttoact_mclk = max(picos_to_mclk(ctrl_num, common_dimm->trrds_ps), 4U);
 582         wrtord_mclk = max(2U, picos_to_mclk(ctrl_num, 2500));
 583         if ((wrrec_mclk < 1) || (wrrec_mclk > 24))
 584                 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
 585         else
 586                 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
 587 #else
 588         refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8;
 589         wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
 590         acttoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trrd_ps);
 591         wrtord_mclk = picos_to_mclk(ctrl_num, common_dimm->twtr_ps);
 592         if ((wrrec_mclk < 1) || (wrrec_mclk > 16))
 593                 printf("Error: WRREC doesn't support %d clocks\n", wrrec_mclk);
 594         else
 595                 wrrec_mclk = wrrec_table[wrrec_mclk - 1];
 596 #endif
 597         if (popts->otf_burst_chop_en)
 598                 wrrec_mclk += 2;
 599
 600         /*
 601          * JEDEC has min requirement for tRRD
 602          */
 603 #if defined(CONFIG_SYS_FSL_DDR3)
 604         if (acttoact_mclk < 4)
 605                 acttoact_mclk = 4;
 606 #endif
 607         /*
 608          * JEDEC has some min requirements for tWTR
 609          */
 610 #if defined(CONFIG_SYS_FSL_DDR2)
 611         if (wrtord_mclk < 2)
 612                 wrtord_mclk = 2;
 613 #elif defined(CONFIG_SYS_FSL_DDR3)
 614         if (wrtord_mclk < 4)
 615                 wrtord_mclk = 4;
 616 #endif
 617         if (popts->otf_burst_chop_en)
 618                 wrtord_mclk += 2;
 619
 620         ddr->timing_cfg_1 = (0
 621                 | ((pretoact_mclk & 0x0F) << 28)
 622                 | ((acttopre_mclk & 0x0F) << 24)
 623                 | ((acttorw_mclk & 0xF) << 20)
 624                 | ((caslat_ctrl & 0xF) << 16)
 625                 | ((refrec_ctrl & 0xF) << 12)
 626                 | ((wrrec_mclk & 0x0F) << 8)
 627                 | ((acttoact_mclk & 0x0F) << 4)
 628                 | ((wrtord_mclk & 0x0F) << 0)
 629                 );
 630         debug("FSLDDR: timing_cfg_1 = 0x%08x\n", ddr->timing_cfg_1);
 631 }
 632
 633 /* DDR SDRAM Timing Configuration 2 (TIMING_CFG_2) */
 634 static void set_timing_cfg_2(const unsigned int ctrl_num,
 635                              fsl_ddr_cfg_regs_t *ddr,
 636                              const memctl_options_t *popts,
 637                              const common_timing_params_t *common_dimm,
 638                              unsigned int cas_latency,
 639                              unsigned int additive_latency)
 640 {
 641         /* Additive latency */
 642         unsigned char add_lat_mclk;
 643         /* CAS-to-preamble override */
 644         unsigned short cpo;
 645         /* Write latency */
 646         unsigned char wr_lat;
 647         /*  Read to precharge (tRTP) */
 648         unsigned char rd_to_pre;
 649         /* Write command to write data strobe timing adjustment */
 650         unsigned char wr_data_delay;
 651         /* Minimum CKE pulse width (tCKE) */
 652         unsigned char cke_pls;
 653         /* Window for four activates (tFAW) */
 654         unsigned short four_act;
 655 #ifdef CONFIG_SYS_FSL_DDR3
 656         const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 657 #endif
 658
 659         /* FIXME add check that this must be less than acttorw_mclk */
 660         add_lat_mclk = additive_latency;
 661         cpo = popts->cpo_override;
 662
 663 #if defined(CONFIG_SYS_FSL_DDR1)
 664         /*
 665          * This is a lie.  It should really be 1, but if it is
 666          * set to 1, bits overlap into the old controller's
 667          * otherwise unused ACSM field.  If we leave it 0, then
 668          * the HW will magically treat it as 1 for DDR 1.  Oh Yea.
 669          */
 670         wr_lat = 0;
 671 #elif defined(CONFIG_SYS_FSL_DDR2)
 672         wr_lat = cas_latency - 1;
 673 #else
 674         wr_lat = compute_cas_write_latency(ctrl_num);
 675 #endif
 676
 677 #ifdef CONFIG_SYS_FSL_DDR4
 678         rd_to_pre = picos_to_mclk(ctrl_num, 7500);
 679 #else
 680         rd_to_pre = picos_to_mclk(ctrl_num, common_dimm->trtp_ps);
 681 #endif
 682         /*
 683          * JEDEC has some min requirements for tRTP
 684          */
 685 #if defined(CONFIG_SYS_FSL_DDR2)
 686         if (rd_to_pre  < 2)
 687                 rd_to_pre  = 2;
 688 #elif defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 689         if (rd_to_pre < 4)
 690                 rd_to_pre = 4;
 691 #endif
 692         if (popts->otf_burst_chop_en)
 693                 rd_to_pre += 2; /* according to UM */
 694
 695         wr_data_delay = popts->write_data_delay;
 696 #ifdef CONFIG_SYS_FSL_DDR4
 697         cpo = 0;
 698         cke_pls = max(3U, picos_to_mclk(ctrl_num, 5000));
 699 #elif defined(CONFIG_SYS_FSL_DDR3)
 700         /*
 701          * cke pulse = max(3nCK, 7.5ns) for DDR3-800
 702          *             max(3nCK, 5.625ns) for DDR3-1066, 1333
 703          *             max(3nCK, 5ns) for DDR3-1600, 1866, 2133
 704          */
 705         cke_pls = max(3U, picos_to_mclk(ctrl_num, mclk_ps > 1870 ? 7500 :
 706                                         (mclk_ps > 1245 ? 5625 : 5000)));
 707 #else
 708         cke_pls = FSL_DDR_MIN_TCKE_PULSE_WIDTH_DDR;
 709 #endif
 710         four_act = picos_to_mclk(ctrl_num,
 711                                  popts->tfaw_window_four_activates_ps);
 712
 713         ddr->timing_cfg_2 = (0
 714                 | ((add_lat_mclk & 0xf) << 28)
 715                 | ((cpo & 0x1f) << 23)
 716                 | ((wr_lat & 0xf) << 19)
 717                 | (((wr_lat & 0x10) >> 4) << 18)
 718                 | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT)
 719                 | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT)
 720                 | ((cke_pls & 0x7) << 6)
 721                 | ((four_act & 0x3f) << 0)
 722                 );
 723         debug("FSLDDR: timing_cfg_2 = 0x%08x\n", ddr->timing_cfg_2);
 724 }
 725
 726 /* DDR SDRAM Register Control Word */
 727 static void set_ddr_sdram_rcw(fsl_ddr_cfg_regs_t *ddr,
 728                                const memctl_options_t *popts,
 729                                const common_timing_params_t *common_dimm)
 730 {
 731         if (common_dimm->all_dimms_registered &&
 732             !common_dimm->all_dimms_unbuffered) {
 733                 if (popts->rcw_override) {
 734                         ddr->ddr_sdram_rcw_1 = popts->rcw_1;
 735                         ddr->ddr_sdram_rcw_2 = popts->rcw_2;
 736                         ddr->ddr_sdram_rcw_3 = popts->rcw_3;
 737                 } else {
 738                         ddr->ddr_sdram_rcw_1 =
 739                                 common_dimm->rcw[0] << 28 | \
 740                                 common_dimm->rcw[1] << 24 | \
 741                                 common_dimm->rcw[2] << 20 | \
 742                                 common_dimm->rcw[3] << 16 | \
 743                                 common_dimm->rcw[4] << 12 | \
 744                                 common_dimm->rcw[5] << 8 | \
 745                                 common_dimm->rcw[6] << 4 | \
 746                                 common_dimm->rcw[7];
 747                         ddr->ddr_sdram_rcw_2 =
 748                                 common_dimm->rcw[8] << 28 | \
 749                                 common_dimm->rcw[9] << 24 | \
 750                                 common_dimm->rcw[10] << 20 | \
 751                                 common_dimm->rcw[11] << 16 | \
 752                                 common_dimm->rcw[12] << 12 | \
 753                                 common_dimm->rcw[13] << 8 | \
 754                                 common_dimm->rcw[14] << 4 | \
 755                                 common_dimm->rcw[15];
 756                 }
 757                 debug("FSLDDR: ddr_sdram_rcw_1 = 0x%08x\n",
 758                       ddr->ddr_sdram_rcw_1);
 759                 debug("FSLDDR: ddr_sdram_rcw_2 = 0x%08x\n",
 760                       ddr->ddr_sdram_rcw_2);
 761                 debug("FSLDDR: ddr_sdram_rcw_3 = 0x%08x\n",
 762                       ddr->ddr_sdram_rcw_3);
 763         }
 764 }
 765
 766 /* DDR SDRAM control configuration (DDR_SDRAM_CFG) */
 767 static void set_ddr_sdram_cfg(fsl_ddr_cfg_regs_t *ddr,
 768                                const memctl_options_t *popts,
 769                                const common_timing_params_t *common_dimm)
 770 {
 771         unsigned int mem_en;            /* DDR SDRAM interface logic enable */
 772         unsigned int sren;              /* Self refresh enable (during sleep) */
 773         unsigned int ecc_en;            /* ECC enable. */
 774         unsigned int rd_en;             /* Registered DIMM enable */
 775         unsigned int sdram_type;        /* Type of SDRAM */
 776         unsigned int dyn_pwr;           /* Dynamic power management mode */
 777         unsigned int dbw;               /* DRAM dta bus width */
 778         unsigned int eight_be = 0;      /* 8-beat burst enable, DDR2 is zero */
 779         unsigned int ncap = 0;          /* Non-concurrent auto-precharge */
 780         unsigned int threet_en;         /* Enable 3T timing */
 781         unsigned int twot_en;           /* Enable 2T timing */
 782         unsigned int ba_intlv_ctl;      /* Bank (CS) interleaving control */
 783         unsigned int x32_en = 0;        /* x32 enable */
 784         unsigned int pchb8 = 0;         /* precharge bit 8 enable */
 785         unsigned int hse;               /* Global half strength override */
 786         unsigned int acc_ecc_en = 0;    /* Accumulated ECC enable */
 787         unsigned int mem_halt = 0;      /* memory controller halt */
 788         unsigned int bi = 0;            /* Bypass initialization */
 789
 790         mem_en = 1;
 791         sren = popts->self_refresh_in_sleep;
 792         if (common_dimm->all_dimms_ecc_capable) {
 793                 /* Allow setting of ECC only if all DIMMs are ECC. */
 794                 ecc_en = popts->ecc_mode;
 795         } else {
 796                 ecc_en = 0;
 797         }
 798
 799         if (common_dimm->all_dimms_registered &&
 800             !common_dimm->all_dimms_unbuffered) {
 801                 rd_en = 1;
 802                 twot_en = 0;
 803         } else {
 804                 rd_en = 0;
 805                 twot_en = popts->twot_en;
 806         }
 807
 808         sdram_type = CONFIG_FSL_SDRAM_TYPE;
 809
 810         dyn_pwr = popts->dynamic_power;
 811         dbw = popts->data_bus_width;
 812         /* 8-beat burst enable DDR-III case
 813          * we must clear it when use the on-the-fly mode,
 814          * must set it when use the 32-bits bus mode.
 815          */
 816         if ((sdram_type == SDRAM_TYPE_DDR3) ||
 817             (sdram_type == SDRAM_TYPE_DDR4)) {
 818                 if (popts->burst_length == DDR_BL8)
 819                         eight_be = 1;
 820                 if (popts->burst_length == DDR_OTF)
 821                         eight_be = 0;
 822                 if (dbw == 0x1)
 823                         eight_be = 1;
 824         }
 825
 826         threet_en = popts->threet_en;
 827         ba_intlv_ctl = popts->ba_intlv_ctl;
 828         hse = popts->half_strength_driver_enable;
 829
 830         /* set when ddr bus width < 64 */
 831         acc_ecc_en = (dbw != 0 && ecc_en == 1) ? 1 : 0;
 832
 833         ddr->ddr_sdram_cfg = (0
 834                         | ((mem_en & 0x1) << 31)
 835                         | ((sren & 0x1) << 30)
 836                         | ((ecc_en & 0x1) << 29)
 837                         | ((rd_en & 0x1) << 28)
 838                         | ((sdram_type & 0x7) << 24)
 839                         | ((dyn_pwr & 0x1) << 21)
 840                         | ((dbw & 0x3) << 19)
 841                         | ((eight_be & 0x1) << 18)
 842                         | ((ncap & 0x1) << 17)
 843                         | ((threet_en & 0x1) << 16)
 844                         | ((twot_en & 0x1) << 15)
 845                         | ((ba_intlv_ctl & 0x7F) << 8)
 846                         | ((x32_en & 0x1) << 5)
 847                         | ((pchb8 & 0x1) << 4)
 848                         | ((hse & 0x1) << 3)
 849                         | ((acc_ecc_en & 0x1) << 2)
 850                         | ((mem_halt & 0x1) << 1)
 851                         | ((bi & 0x1) << 0)
 852                         );
 853         debug("FSLDDR: ddr_sdram_cfg = 0x%08x\n", ddr->ddr_sdram_cfg);
 854 }
 855
 856 /* DDR SDRAM control configuration 2 (DDR_SDRAM_CFG_2) */
 857 static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num,
 858                                fsl_ddr_cfg_regs_t *ddr,
 859                                const memctl_options_t *popts,
 860                                const unsigned int unq_mrs_en)
 861 {
 862         unsigned int frc_sr = 0;        /* Force self refresh */
 863         unsigned int sr_ie = 0;         /* Self-refresh interrupt enable */
 864         unsigned int odt_cfg = 0;       /* ODT configuration */
 865         unsigned int num_pr;            /* Number of posted refreshes */
 866         unsigned int slow = 0;          /* DDR will be run less than 1250 */
 867         unsigned int x4_en = 0;         /* x4 DRAM enable */
 868         unsigned int obc_cfg;           /* On-The-Fly Burst Chop Cfg */
 869         unsigned int ap_en;             /* Address Parity Enable */
 870         unsigned int d_init;            /* DRAM data initialization */
 871         unsigned int rcw_en = 0;        /* Register Control Word Enable */
 872         unsigned int md_en = 0;         /* Mirrored DIMM Enable */
 873         unsigned int qd_en = 0;         /* quad-rank DIMM Enable */
 874         int i;
 875 #ifndef CONFIG_SYS_FSL_DDR4
 876         unsigned int dll_rst_dis = 1;   /* DLL reset disable */
 877         unsigned int dqs_cfg;           /* DQS configuration */
 878
 879         dqs_cfg = popts->dqs_config;
 880 #endif
 881         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
 882                 if (popts->cs_local_opts[i].odt_rd_cfg
 883                         || popts->cs_local_opts[i].odt_wr_cfg) {
 884                         odt_cfg = SDRAM_CFG2_ODT_ONLY_READ;
 885                         break;
 886                 }
 887         }
 888         sr_ie = popts->self_refresh_interrupt_en;
 889         num_pr = popts->package_3ds + 1;
 890
 891         /*
 892          * 8572 manual says
 893          *     {TIMING_CFG_1[PRETOACT]
 894          *      + [DDR_SDRAM_CFG_2[NUM_PR]
 895          *        * ({EXT_REFREC || REFREC} + 8 + 2)]}
 896          *      << DDR_SDRAM_INTERVAL[REFINT]
 897          */
 898 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 899         obc_cfg = popts->otf_burst_chop_en;
 900 #else
 901         obc_cfg = 0;
 902 #endif
 903
 904 #if (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7)
 905         slow = get_ddr_freq(ctrl_num) < 1249000000;
 906 #endif
 907
 908         if (popts->registered_dimm_en)
 909                 rcw_en = 1;
 910
 911         /* DDR4 can have address parity for UDIMM and discrete */
 912         if ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) &&
 913             (!popts->registered_dimm_en)) {
 914                 ap_en = 0;
 915         } else {
 916                 ap_en = popts->ap_en;
 917         }
 918
 919         x4_en = popts->x4_en ? 1 : 0;
 920
 921 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 922         /* Use the DDR controller to auto initialize memory. */
 923         d_init = popts->ecc_init_using_memctl;
 924         ddr->ddr_data_init = CONFIG_MEM_INIT_VALUE;
 925         debug("DDR: ddr_data_init = 0x%08x\n", ddr->ddr_data_init);
 926 #else
 927         /* Memory will be initialized via DMA, or not at all. */
 928         d_init = 0;
 929 #endif
 930
 931 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
 932         md_en = popts->mirrored_dimm;
 933 #endif
 934         qd_en = popts->quad_rank_present ? 1 : 0;
 935         ddr->ddr_sdram_cfg_2 = (0
 936                 | ((frc_sr & 0x1) << 31)
 937                 | ((sr_ie & 0x1) << 30)
 938 #ifndef CONFIG_SYS_FSL_DDR4
 939                 | ((dll_rst_dis & 0x1) << 29)
 940                 | ((dqs_cfg & 0x3) << 26)
 941 #endif
 942                 | ((odt_cfg & 0x3) << 21)
 943                 | ((num_pr & 0xf) << 12)
 944                 | ((slow & 1) << 11)
 945                 | (x4_en << 10)
 946                 | (qd_en << 9)
 947                 | (unq_mrs_en << 8)
 948                 | ((obc_cfg & 0x1) << 6)
 949                 | ((ap_en & 0x1) << 5)
 950                 | ((d_init & 0x1) << 4)
 951                 | ((rcw_en & 0x1) << 2)
 952                 | ((md_en & 0x1) << 0)
 953                 );
 954         debug("FSLDDR: ddr_sdram_cfg_2 = 0x%08x\n", ddr->ddr_sdram_cfg_2);
 955 }
 956
 957 #ifdef CONFIG_SYS_FSL_DDR4
 958 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
 959 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
 960                                 fsl_ddr_cfg_regs_t *ddr,
 961                                 const memctl_options_t *popts,
 962                                 const common_timing_params_t *common_dimm,
 963                                 const unsigned int unq_mrs_en)
 964 {
 965         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
 966         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
 967         int i;
 968         unsigned int wr_crc = 0;        /* Disable */
 969         unsigned int rtt_wr = 0;        /* Rtt_WR - dynamic ODT off */
 970         unsigned int srt = 0;   /* self-refresh temerature, normal range */
 971         unsigned int cwl = compute_cas_write_latency(ctrl_num) - 9;
 972         unsigned int mpr = 0;   /* serial */
 973         unsigned int wc_lat;
 974         const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
 975
 976         if (popts->rtt_override)
 977                 rtt_wr = popts->rtt_wr_override_value;
 978         else
 979                 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
 980
 981         if (common_dimm->extended_op_srt)
 982                 srt = common_dimm->extended_op_srt;
 983
 984         esdmode2 = (0
 985                 | ((wr_crc & 0x1) << 12)
 986                 | ((rtt_wr & 0x3) << 9)
 987                 | ((srt & 0x3) << 6)
 988                 | ((cwl & 0x7) << 3));
 989
 990         if (mclk_ps >= 1250)
 991                 wc_lat = 0;
 992         else if (mclk_ps >= 833)
 993                 wc_lat = 1;
 994         else
 995                 wc_lat = 2;
 996
 997         esdmode3 = (0
 998                 | ((mpr & 0x3) << 11)
 999                 | ((wc_lat & 0x3) << 9));
1000
1001         ddr->ddr_sdram_mode_2 = (0
1002                                  | ((esdmode2 & 0xFFFF) << 16)
1003                                  | ((esdmode3 & 0xFFFF) << 0)
1004                                  );
1005         debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1006
1007         if (unq_mrs_en) {       /* unique mode registers are supported */
1008                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1009                         if (popts->rtt_override)
1010                                 rtt_wr = popts->rtt_wr_override_value;
1011                         else
1012                                 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
1013
1014                         esdmode2 &= 0xF9FF;     /* clear bit 10, 9 */
1015                         esdmode2 |= (rtt_wr & 0x3) << 9;
1016                         switch (i) {
1017                         case 1:
1018                                 ddr->ddr_sdram_mode_4 = (0
1019                                         | ((esdmode2 & 0xFFFF) << 16)
1020                                         | ((esdmode3 & 0xFFFF) << 0)
1021                                         );
1022                                 break;
1023                         case 2:
1024                                 ddr->ddr_sdram_mode_6 = (0
1025                                         | ((esdmode2 & 0xFFFF) << 16)
1026                                         | ((esdmode3 & 0xFFFF) << 0)
1027                                         );
1028                                 break;
1029                         case 3:
1030                                 ddr->ddr_sdram_mode_8 = (0
1031                                         | ((esdmode2 & 0xFFFF) << 16)
1032                                         | ((esdmode3 & 0xFFFF) << 0)
1033                                         );
1034                                 break;
1035                         }
1036                 }
1037                 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
1038                       ddr->ddr_sdram_mode_4);
1039                 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
1040                       ddr->ddr_sdram_mode_6);
1041                 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
1042                       ddr->ddr_sdram_mode_8);
1043         }
1044 }
1045 #elif defined(CONFIG_SYS_FSL_DDR3)
1046 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
1047 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
1048                                 fsl_ddr_cfg_regs_t *ddr,
1049                                 const memctl_options_t *popts,
1050                                 const common_timing_params_t *common_dimm,
1051                                 const unsigned int unq_mrs_en)
1052 {
1053         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
1054         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
1055         int i;
1056         unsigned int rtt_wr = 0;        /* Rtt_WR - dynamic ODT off */
1057         unsigned int srt = 0;   /* self-refresh temerature, normal range */
1058         unsigned int asr = 0;   /* auto self-refresh disable */
1059         unsigned int cwl = compute_cas_write_latency(ctrl_num) - 5;
1060         unsigned int pasr = 0;  /* partial array self refresh disable */
1061
1062         if (popts->rtt_override)
1063                 rtt_wr = popts->rtt_wr_override_value;
1064         else
1065                 rtt_wr = popts->cs_local_opts[0].odt_rtt_wr;
1066
1067         if (common_dimm->extended_op_srt)
1068                 srt = common_dimm->extended_op_srt;
1069
1070         esdmode2 = (0
1071                 | ((rtt_wr & 0x3) << 9)
1072                 | ((srt & 0x1) << 7)
1073                 | ((asr & 0x1) << 6)
1074                 | ((cwl & 0x7) << 3)
1075                 | ((pasr & 0x7) << 0));
1076         ddr->ddr_sdram_mode_2 = (0
1077                                  | ((esdmode2 & 0xFFFF) << 16)
1078                                  | ((esdmode3 & 0xFFFF) << 0)
1079                                  );
1080         debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1081
1082         if (unq_mrs_en) {       /* unique mode registers are supported */
1083                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1084                         if (popts->rtt_override)
1085                                 rtt_wr = popts->rtt_wr_override_value;
1086                         else
1087                                 rtt_wr = popts->cs_local_opts[i].odt_rtt_wr;
1088
1089                         esdmode2 &= 0xF9FF;     /* clear bit 10, 9 */
1090                         esdmode2 |= (rtt_wr & 0x3) << 9;
1091                         switch (i) {
1092                         case 1:
1093                                 ddr->ddr_sdram_mode_4 = (0
1094                                         | ((esdmode2 & 0xFFFF) << 16)
1095                                         | ((esdmode3 & 0xFFFF) << 0)
1096                                         );
1097                                 break;
1098                         case 2:
1099                                 ddr->ddr_sdram_mode_6 = (0
1100                                         | ((esdmode2 & 0xFFFF) << 16)
1101                                         | ((esdmode3 & 0xFFFF) << 0)
1102                                         );
1103                                 break;
1104                         case 3:
1105                                 ddr->ddr_sdram_mode_8 = (0
1106                                         | ((esdmode2 & 0xFFFF) << 16)
1107                                         | ((esdmode3 & 0xFFFF) << 0)
1108                                         );
1109                                 break;
1110                         }
1111                 }
1112                 debug("FSLDDR: ddr_sdram_mode_4 = 0x%08x\n",
1113                         ddr->ddr_sdram_mode_4);
1114                 debug("FSLDDR: ddr_sdram_mode_6 = 0x%08x\n",
1115                         ddr->ddr_sdram_mode_6);
1116                 debug("FSLDDR: ddr_sdram_mode_8 = 0x%08x\n",
1117                         ddr->ddr_sdram_mode_8);
1118         }
1119 }
1120
1121 #else /* for DDR2 and DDR1 */
1122 /* DDR SDRAM Mode configuration 2 (DDR_SDRAM_MODE_2) */
1123 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num,
1124                                 fsl_ddr_cfg_regs_t *ddr,
1125                                 const memctl_options_t *popts,
1126                                 const common_timing_params_t *common_dimm,
1127                                 const unsigned int unq_mrs_en)
1128 {
1129         unsigned short esdmode2 = 0;    /* Extended SDRAM mode 2 */
1130         unsigned short esdmode3 = 0;    /* Extended SDRAM mode 3 */
1131
1132         ddr->ddr_sdram_mode_2 = (0
1133                                  | ((esdmode2 & 0xFFFF) << 16)
1134                                  | ((esdmode3 & 0xFFFF) << 0)
1135                                  );
1136         debug("FSLDDR: ddr_sdram_mode_2 = 0x%08x\n", ddr->ddr_sdram_mode_2);
1137 }
1138 #endif
1139
1140 #ifdef CONFIG_SYS_FSL_DDR4
1141 /* DDR SDRAM Mode configuration 9 (DDR_SDRAM_MODE_9) */
1142 static void set_ddr_sdram_mode_9(fsl_ddr_cfg_regs_t *ddr,
1143                                 const memctl_options_t *popts,
1144                                 const common_timing_params_t *common_dimm,
1145                                 const unsigned int unq_mrs_en)
1146 {
1147         int i;
1148         unsigned short esdmode4 = 0;    /* Extended SDRAM mode 4 */
1149         unsigned short esdmode5;        /* Extended SDRAM mode 5 */
1150         int rtt_park = 0;
1151         bool four_cs = false;
1152         const unsigned int mclk_ps = get_memory_clk_period_ps(0);
1153
1154 #if CONFIG_CHIP_SELECTS_PER_CTRL == 4
1155         if ((ddr->cs[0].config & SDRAM_CS_CONFIG_EN) &&
1156             (ddr->cs[1].config & SDRAM_CS_CONFIG_EN) &&
1157             (ddr->cs[2].config & SDRAM_CS_CONFIG_EN) &&
1158             (ddr->cs[3].config & SDRAM_CS_CONFIG_EN))
1159                 four_cs = true;
1160 #endif
1161         if (ddr->cs[0].config & SDRAM_CS_CONFIG_EN) {
1162                 esdmode5 = 0x00000500;  /* Data mask enable, RTT_PARK CS0 */
1163                 rtt_park = four_cs ? 0 : 1;
1164         } else {
1165                 esdmode5 = 0x00000400;  /* Data mask enabled */
1166         }
1167
1168         /*
1169          * For DDR3, set C/A latency if address parity is enabled.
1170          * For DDR4, set C/A latency for UDIMM only. For RDIMM the delay is
1171          * handled by register chip and RCW settings.
1172          */
1173         if ((ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) &&
1174             ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) ||
1175              !popts->registered_dimm_en)) {
1176                 if (mclk_ps >= 935) {
1177                         /* for DDR4-1600/1866/2133 */
1178                         esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK;
1179                 } else if (mclk_ps >= 833) {
1180                         /* for DDR4-2400 */
1181                         esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK;
1182                 } else {
1183                         printf("parity: mclk_ps = %d not supported\n", mclk_ps);
1184                 }
1185         }
1186
1187         ddr->ddr_sdram_mode_9 = (0
1188                                  | ((esdmode4 & 0xffff) << 16)
1189                                  | ((esdmode5 & 0xffff) << 0)
1190                                 );
1191
1192         /* Normally only the first enabled CS use 0x500, others use 0x400
1193          * But when four chip-selects are all enabled, all mode registers
1194          * need 0x500 to park.
1195          */
1196
1197         debug("FSLDDR: ddr_sdram_mode_9 = 0x%08x\n", ddr->ddr_sdram_mode_9);
1198         if (unq_mrs_en) {       /* unique mode registers are supported */
1199                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1200                         if (!rtt_park &&
1201                             (ddr->cs[i].config & SDRAM_CS_CONFIG_EN)) {
1202                                 esdmode5 |= 0x00000500; /* RTT_PARK */
1203                                 rtt_park = four_cs ? 0 : 1;
1204                         } else {
1205                                 esdmode5 = 0x00000400;
1206                         }
1207
1208                         if ((ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) &&
1209                             ((CONFIG_FSL_SDRAM_TYPE != SDRAM_TYPE_DDR4) ||
1210                              !popts->registered_dimm_en)) {
1211                                 if (mclk_ps >= 935) {
1212                                         /* for DDR4-1600/1866/2133 */
1213                                         esdmode5 |= DDR_MR5_CA_PARITY_LAT_4_CLK;
1214                                 } else if (mclk_ps >= 833) {
1215                                         /* for DDR4-2400 */
1216                                         esdmode5 |= DDR_MR5_CA_PARITY_LAT_5_CLK;
1217                                 } else {
1218                                         printf("parity: mclk_ps = %d not supported\n",
1219                                                mclk_ps);
1220                                 }
1221                         }
1222
1223                         switch (i) {
1224                         case 1:
1225                                 ddr->ddr_sdram_mode_11 = (0
1226                                         | ((esdmode4 & 0xFFFF) << 16)
1227                                         | ((esdmode5 & 0xFFFF) << 0)
1228                                         );
1229                                 break;
1230                         case 2:
1231                                 ddr->ddr_sdram_mode_13 = (0
1232                                         | ((esdmode4 & 0xFFFF) << 16)
1233                                         | ((esdmode5 & 0xFFFF) << 0)
1234                                         );
1235                                 break;
1236                         case 3:
1237                                 ddr->ddr_sdram_mode_15 = (0
1238                                         | ((esdmode4 & 0xFFFF) << 16)
1239                                         | ((esdmode5 & 0xFFFF) << 0)
1240                                         );
1241                                 break;
1242                         }
1243                 }
1244                 debug("FSLDDR: ddr_sdram_mode_11 = 0x%08x\n",
1245                       ddr->ddr_sdram_mode_11);
1246                 debug("FSLDDR: ddr_sdram_mode_13 = 0x%08x\n",
1247                       ddr->ddr_sdram_mode_13);
1248                 debug("FSLDDR: ddr_sdram_mode_15 = 0x%08x\n",
1249                       ddr->ddr_sdram_mode_15);
1250         }
1251 }
1252
1253 /* DDR SDRAM Mode configuration 10 (DDR_SDRAM_MODE_10) */
1254 static void set_ddr_sdram_mode_10(const unsigned int ctrl_num,
1255                                 fsl_ddr_cfg_regs_t *ddr,
1256                                 const memctl_options_t *popts,
1257                                 const common_timing_params_t *common_dimm,
1258                                 const unsigned int unq_mrs_en)
1259 {
1260         int i;
1261         unsigned short esdmode6 = 0;    /* Extended SDRAM mode 6 */
1262         unsigned short esdmode7 = 0;    /* Extended SDRAM mode 7 */
1263         unsigned int tccdl_min = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
1264
1265         esdmode6 = ((tccdl_min - 4) & 0x7) << 10;
1266
1267         if (popts->ddr_cdr2 & DDR_CDR2_VREF_RANGE_2)
1268                 esdmode6 |= 1 << 6;     /* Range 2 */
1269
1270         ddr->ddr_sdram_mode_10 = (0
1271                                  | ((esdmode6 & 0xffff) << 16)
1272                                  | ((esdmode7 & 0xffff) << 0)
1273                                 );
1274         debug("FSLDDR: ddr_sdram_mode_10 = 0x%08x\n", ddr->ddr_sdram_mode_10);
1275         if (unq_mrs_en) {       /* unique mode registers are supported */
1276                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1277                         switch (i) {
1278                         case 1:
1279                                 ddr->ddr_sdram_mode_12 = (0
1280                                         | ((esdmode6 & 0xFFFF) << 16)
1281                                         | ((esdmode7 & 0xFFFF) << 0)
1282                                         );
1283                                 break;
1284                         case 2:
1285                                 ddr->ddr_sdram_mode_14 = (0
1286                                         | ((esdmode6 & 0xFFFF) << 16)
1287                                         | ((esdmode7 & 0xFFFF) << 0)
1288                                         );
1289                                 break;
1290                         case 3:
1291                                 ddr->ddr_sdram_mode_16 = (0
1292                                         | ((esdmode6 & 0xFFFF) << 16)
1293                                         | ((esdmode7 & 0xFFFF) << 0)
1294                                         );
1295                                 break;
1296                         }
1297                 }
1298                 debug("FSLDDR: ddr_sdram_mode_12 = 0x%08x\n",
1299                       ddr->ddr_sdram_mode_12);
1300                 debug("FSLDDR: ddr_sdram_mode_14 = 0x%08x\n",
1301                       ddr->ddr_sdram_mode_14);
1302                 debug("FSLDDR: ddr_sdram_mode_16 = 0x%08x\n",
1303                       ddr->ddr_sdram_mode_16);
1304         }
1305 }
1306
1307 #endif
1308
1309 /* DDR SDRAM Interval Configuration (DDR_SDRAM_INTERVAL) */
1310 static void set_ddr_sdram_interval(const unsigned int ctrl_num,
1311                                 fsl_ddr_cfg_regs_t *ddr,
1312                                 const memctl_options_t *popts,
1313                                 const common_timing_params_t *common_dimm)
1314 {
1315         unsigned int refint;    /* Refresh interval */
1316         unsigned int bstopre;   /* Precharge interval */
1317
1318         refint = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps);
1319
1320         bstopre = popts->bstopre;
1321
1322         /* refint field used 0x3FFF in earlier controllers */
1323         ddr->ddr_sdram_interval = (0
1324                                    | ((refint & 0xFFFF) << 16)
1325                                    | ((bstopre & 0x3FFF) << 0)
1326                                    );
1327         debug("FSLDDR: ddr_sdram_interval = 0x%08x\n", ddr->ddr_sdram_interval);
1328 }
1329
1330 #ifdef CONFIG_SYS_FSL_DDR4
1331 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1332 static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1333                                fsl_ddr_cfg_regs_t *ddr,
1334                                const memctl_options_t *popts,
1335                                const common_timing_params_t *common_dimm,
1336                                unsigned int cas_latency,
1337                                unsigned int additive_latency,
1338                                const unsigned int unq_mrs_en)
1339 {
1340         int i;
1341         unsigned short esdmode;         /* Extended SDRAM mode */
1342         unsigned short sdmode;          /* SDRAM mode */
1343
1344         /* Mode Register - MR1 */
1345         unsigned int qoff = 0;          /* Output buffer enable 0=yes, 1=no */
1346         unsigned int tdqs_en = 0;       /* TDQS Enable: 0=no, 1=yes */
1347         unsigned int rtt;
1348         unsigned int wrlvl_en = 0;      /* Write level enable: 0=no, 1=yes */
1349         unsigned int al = 0;            /* Posted CAS# additive latency (AL) */
1350         unsigned int dic = 0;           /* Output driver impedance, 40ohm */
1351         unsigned int dll_en = 1;        /* DLL Enable  1=Enable (Normal),
1352                                                        0=Disable (Test/Debug) */
1353
1354         /* Mode Register - MR0 */
1355         unsigned int wr = 0;    /* Write Recovery */
1356         unsigned int dll_rst;   /* DLL Reset */
1357         unsigned int mode;      /* Normal=0 or Test=1 */
1358         unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1359         /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1360         unsigned int bt;
1361         unsigned int bl;        /* BL: Burst Length */
1362
1363         unsigned int wr_mclk;
1364         /* DDR4 support WR 10, 12, 14, 16, 18, 20, 24 */
1365         static const u8 wr_table[] = {
1366                 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 6, 6};
1367         /* DDR4 support CAS 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 22, 24 */
1368         static const u8 cas_latency_table[] = {
1369                 0, 1, 2, 3, 4, 5, 6, 7, 8, 8,
1370                 9, 9, 10, 10, 11, 11};
1371
1372         if (popts->rtt_override)
1373                 rtt = popts->rtt_override_value;
1374         else
1375                 rtt = popts->cs_local_opts[0].odt_rtt_norm;
1376
1377         if (additive_latency == (cas_latency - 1))
1378                 al = 1;
1379         if (additive_latency == (cas_latency - 2))
1380                 al = 2;
1381
1382         if (popts->quad_rank_present)
1383                 dic = 1;        /* output driver impedance 240/7 ohm */
1384
1385         /*
1386          * The esdmode value will also be used for writing
1387          * MR1 during write leveling for DDR3, although the
1388          * bits specifically related to the write leveling
1389          * scheme will be handled automatically by the DDR
1390          * controller. so we set the wrlvl_en = 0 here.
1391          */
1392         esdmode = (0
1393                 | ((qoff & 0x1) << 12)
1394                 | ((tdqs_en & 0x1) << 11)
1395                 | ((rtt & 0x7) << 8)
1396                 | ((wrlvl_en & 0x1) << 7)
1397                 | ((al & 0x3) << 3)
1398                 | ((dic & 0x3) << 1)   /* DIC field is split */
1399                 | ((dll_en & 0x1) << 0)
1400                 );
1401
1402         /*
1403          * DLL control for precharge PD
1404          * 0=slow exit DLL off (tXPDLL)
1405          * 1=fast exit DLL on (tXP)
1406          */
1407
1408         wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
1409         if (wr_mclk <= 24) {
1410                 wr = wr_table[wr_mclk - 10];
1411         } else {
1412                 printf("Error: unsupported write recovery for mode register wr_mclk = %d\n",
1413                        wr_mclk);
1414         }
1415
1416         dll_rst = 0;    /* dll no reset */
1417         mode = 0;       /* normal mode */
1418
1419         /* look up table to get the cas latency bits */
1420         if (cas_latency >= 9 && cas_latency <= 24)
1421                 caslat = cas_latency_table[cas_latency - 9];
1422         else
1423                 printf("Error: unsupported cas latency for mode register\n");
1424
1425         bt = 0; /* Nibble sequential */
1426
1427         switch (popts->burst_length) {
1428         case DDR_BL8:
1429                 bl = 0;
1430                 break;
1431         case DDR_OTF:
1432                 bl = 1;
1433                 break;
1434         case DDR_BC4:
1435                 bl = 2;
1436                 break;
1437         default:
1438                 printf("Error: invalid burst length of %u specified. ",
1439                        popts->burst_length);
1440                 puts("Defaulting to on-the-fly BC4 or BL8 beats.\n");
1441                 bl = 1;
1442                 break;
1443         }
1444
1445         sdmode = (0
1446                   | ((wr & 0x7) << 9)
1447                   | ((dll_rst & 0x1) << 8)
1448                   | ((mode & 0x1) << 7)
1449                   | (((caslat >> 1) & 0x7) << 4)
1450                   | ((bt & 0x1) << 3)
1451                   | ((caslat & 1) << 2)
1452                   | ((bl & 0x3) << 0)
1453                   );
1454
1455         ddr->ddr_sdram_mode = (0
1456                                | ((esdmode & 0xFFFF) << 16)
1457                                | ((sdmode & 0xFFFF) << 0)
1458                                );
1459
1460         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1461
1462         if (unq_mrs_en) {       /* unique mode registers are supported */
1463                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1464                         if (popts->rtt_override)
1465                                 rtt = popts->rtt_override_value;
1466                         else
1467                                 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1468
1469                         esdmode &= 0xF8FF;      /* clear bit 10,9,8 for rtt */
1470                         esdmode |= (rtt & 0x7) << 8;
1471                         switch (i) {
1472                         case 1:
1473                                 ddr->ddr_sdram_mode_3 = (0
1474                                        | ((esdmode & 0xFFFF) << 16)
1475                                        | ((sdmode & 0xFFFF) << 0)
1476                                        );
1477                                 break;
1478                         case 2:
1479                                 ddr->ddr_sdram_mode_5 = (0
1480                                        | ((esdmode & 0xFFFF) << 16)
1481                                        | ((sdmode & 0xFFFF) << 0)
1482                                        );
1483                                 break;
1484                         case 3:
1485                                 ddr->ddr_sdram_mode_7 = (0
1486                                        | ((esdmode & 0xFFFF) << 16)
1487                                        | ((sdmode & 0xFFFF) << 0)
1488                                        );
1489                                 break;
1490                         }
1491                 }
1492                 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1493                       ddr->ddr_sdram_mode_3);
1494                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1495                       ddr->ddr_sdram_mode_5);
1496                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1497                       ddr->ddr_sdram_mode_5);
1498         }
1499 }
1500
1501 #elif defined(CONFIG_SYS_FSL_DDR3)
1502 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1503 static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1504                                fsl_ddr_cfg_regs_t *ddr,
1505                                const memctl_options_t *popts,
1506                                const common_timing_params_t *common_dimm,
1507                                unsigned int cas_latency,
1508                                unsigned int additive_latency,
1509                                const unsigned int unq_mrs_en)
1510 {
1511         int i;
1512         unsigned short esdmode;         /* Extended SDRAM mode */
1513         unsigned short sdmode;          /* SDRAM mode */
1514
1515         /* Mode Register - MR1 */
1516         unsigned int qoff = 0;          /* Output buffer enable 0=yes, 1=no */
1517         unsigned int tdqs_en = 0;       /* TDQS Enable: 0=no, 1=yes */
1518         unsigned int rtt;
1519         unsigned int wrlvl_en = 0;      /* Write level enable: 0=no, 1=yes */
1520         unsigned int al = 0;            /* Posted CAS# additive latency (AL) */
1521         unsigned int dic = 0;           /* Output driver impedance, 40ohm */
1522         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
1523                                                        1=Disable (Test/Debug) */
1524
1525         /* Mode Register - MR0 */
1526         unsigned int dll_on;    /* DLL control for precharge PD, 0=off, 1=on */
1527         unsigned int wr = 0;    /* Write Recovery */
1528         unsigned int dll_rst;   /* DLL Reset */
1529         unsigned int mode;      /* Normal=0 or Test=1 */
1530         unsigned int caslat = 4;/* CAS# latency, default set as 6 cycles */
1531         /* BT: Burst Type (0=Nibble Sequential, 1=Interleaved) */
1532         unsigned int bt;
1533         unsigned int bl;        /* BL: Burst Length */
1534
1535         unsigned int wr_mclk;
1536         /*
1537          * DDR_SDRAM_MODE doesn't support 9,11,13,15
1538          * Please refer JEDEC Standard No. 79-3E for Mode Register MR0
1539          * for this table
1540          */
1541         static const u8 wr_table[] = {1, 2, 3, 4, 5, 5, 6, 6, 7, 7, 0, 0};
1542
1543         if (popts->rtt_override)
1544                 rtt = popts->rtt_override_value;
1545         else
1546                 rtt = popts->cs_local_opts[0].odt_rtt_norm;
1547
1548         if (additive_latency == (cas_latency - 1))
1549                 al = 1;
1550         if (additive_latency == (cas_latency - 2))
1551                 al = 2;
1552
1553         if (popts->quad_rank_present)
1554                 dic = 1;        /* output driver impedance 240/7 ohm */
1555
1556         /*
1557          * The esdmode value will also be used for writing
1558          * MR1 during write leveling for DDR3, although the
1559          * bits specifically related to the write leveling
1560          * scheme will be handled automatically by the DDR
1561          * controller. so we set the wrlvl_en = 0 here.
1562          */
1563         esdmode = (0
1564                 | ((qoff & 0x1) << 12)
1565                 | ((tdqs_en & 0x1) << 11)
1566                 | ((rtt & 0x4) << 7)   /* rtt field is split */
1567                 | ((wrlvl_en & 0x1) << 7)
1568                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1569                 | ((dic & 0x2) << 4)   /* DIC field is split */
1570                 | ((al & 0x3) << 3)
1571                 | ((rtt & 0x1) << 2)  /* rtt field is split */
1572                 | ((dic & 0x1) << 1)   /* DIC field is split */
1573                 | ((dll_en & 0x1) << 0)
1574                 );
1575
1576         /*
1577          * DLL control for precharge PD
1578          * 0=slow exit DLL off (tXPDLL)
1579          * 1=fast exit DLL on (tXP)
1580          */
1581         dll_on = 1;
1582
1583         wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
1584         if (wr_mclk <= 16) {
1585                 wr = wr_table[wr_mclk - 5];
1586         } else {
1587                 printf("Error: unsupported write recovery for mode register "
1588                        "wr_mclk = %d\n", wr_mclk);
1589         }
1590
1591         dll_rst = 0;    /* dll no reset */
1592         mode = 0;       /* normal mode */
1593
1594         /* look up table to get the cas latency bits */
1595         if (cas_latency >= 5 && cas_latency <= 16) {
1596                 unsigned char cas_latency_table[] = {
1597                         0x2,    /* 5 clocks */
1598                         0x4,    /* 6 clocks */
1599                         0x6,    /* 7 clocks */
1600                         0x8,    /* 8 clocks */
1601                         0xa,    /* 9 clocks */
1602                         0xc,    /* 10 clocks */
1603                         0xe,    /* 11 clocks */
1604                         0x1,    /* 12 clocks */
1605                         0x3,    /* 13 clocks */
1606                         0x5,    /* 14 clocks */
1607                         0x7,    /* 15 clocks */
1608                         0x9,    /* 16 clocks */
1609                 };
1610                 caslat = cas_latency_table[cas_latency - 5];
1611         } else {
1612                 printf("Error: unsupported cas latency for mode register\n");
1613         }
1614
1615         bt = 0; /* Nibble sequential */
1616
1617         switch (popts->burst_length) {
1618         case DDR_BL8:
1619                 bl = 0;
1620                 break;
1621         case DDR_OTF:
1622                 bl = 1;
1623                 break;
1624         case DDR_BC4:
1625                 bl = 2;
1626                 break;
1627         default:
1628                 printf("Error: invalid burst length of %u specified. "
1629                         " Defaulting to on-the-fly BC4 or BL8 beats.\n",
1630                         popts->burst_length);
1631                 bl = 1;
1632                 break;
1633         }
1634
1635         sdmode = (0
1636                   | ((dll_on & 0x1) << 12)
1637                   | ((wr & 0x7) << 9)
1638                   | ((dll_rst & 0x1) << 8)
1639                   | ((mode & 0x1) << 7)
1640                   | (((caslat >> 1) & 0x7) << 4)
1641                   | ((bt & 0x1) << 3)
1642                   | ((caslat & 1) << 2)
1643                   | ((bl & 0x3) << 0)
1644                   );
1645
1646         ddr->ddr_sdram_mode = (0
1647                                | ((esdmode & 0xFFFF) << 16)
1648                                | ((sdmode & 0xFFFF) << 0)
1649                                );
1650
1651         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1652
1653         if (unq_mrs_en) {       /* unique mode registers are supported */
1654                 for (i = 1; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
1655                         if (popts->rtt_override)
1656                                 rtt = popts->rtt_override_value;
1657                         else
1658                                 rtt = popts->cs_local_opts[i].odt_rtt_norm;
1659
1660                         esdmode &= 0xFDBB;      /* clear bit 9,6,2 */
1661                         esdmode |= (0
1662                                 | ((rtt & 0x4) << 7)   /* rtt field is split */
1663                                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1664                                 | ((rtt & 0x1) << 2)  /* rtt field is split */
1665                                 );
1666                         switch (i) {
1667                         case 1:
1668                                 ddr->ddr_sdram_mode_3 = (0
1669                                        | ((esdmode & 0xFFFF) << 16)
1670                                        | ((sdmode & 0xFFFF) << 0)
1671                                        );
1672                                 break;
1673                         case 2:
1674                                 ddr->ddr_sdram_mode_5 = (0
1675                                        | ((esdmode & 0xFFFF) << 16)
1676                                        | ((sdmode & 0xFFFF) << 0)
1677                                        );
1678                                 break;
1679                         case 3:
1680                                 ddr->ddr_sdram_mode_7 = (0
1681                                        | ((esdmode & 0xFFFF) << 16)
1682                                        | ((sdmode & 0xFFFF) << 0)
1683                                        );
1684                                 break;
1685                         }
1686                 }
1687                 debug("FSLDDR: ddr_sdram_mode_3 = 0x%08x\n",
1688                         ddr->ddr_sdram_mode_3);
1689                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1690                         ddr->ddr_sdram_mode_5);
1691                 debug("FSLDDR: ddr_sdram_mode_5 = 0x%08x\n",
1692                         ddr->ddr_sdram_mode_5);
1693         }
1694 }
1695
1696 #else /* !CONFIG_SYS_FSL_DDR3 */
1697
1698 /* DDR SDRAM Mode configuration set (DDR_SDRAM_MODE) */
1699 static void set_ddr_sdram_mode(const unsigned int ctrl_num,
1700                                fsl_ddr_cfg_regs_t *ddr,
1701                                const memctl_options_t *popts,
1702                                const common_timing_params_t *common_dimm,
1703                                unsigned int cas_latency,
1704                                unsigned int additive_latency,
1705                                const unsigned int unq_mrs_en)
1706 {
1707         unsigned short esdmode;         /* Extended SDRAM mode */
1708         unsigned short sdmode;          /* SDRAM mode */
1709
1710         /*
1711          * FIXME: This ought to be pre-calculated in a
1712          * technology-specific routine,
1713          * e.g. compute_DDR2_mode_register(), and then the
1714          * sdmode and esdmode passed in as part of common_dimm.
1715          */
1716
1717         /* Extended Mode Register */
1718         unsigned int mrs = 0;           /* Mode Register Set */
1719         unsigned int outputs = 0;       /* 0=Enabled, 1=Disabled */
1720         unsigned int rdqs_en = 0;       /* RDQS Enable: 0=no, 1=yes */
1721         unsigned int dqs_en = 0;        /* DQS# Enable: 0=enable, 1=disable */
1722         unsigned int ocd = 0;           /* 0x0=OCD not supported,
1723                                            0x7=OCD default state */
1724         unsigned int rtt;
1725         unsigned int al;                /* Posted CAS# additive latency (AL) */
1726         unsigned int ods = 0;           /* Output Drive Strength:
1727                                                 0 = Full strength (18ohm)
1728                                                 1 = Reduced strength (4ohm) */
1729         unsigned int dll_en = 0;        /* DLL Enable  0=Enable (Normal),
1730                                                        1=Disable (Test/Debug) */
1731
1732         /* Mode Register (MR) */
1733         unsigned int mr;        /* Mode Register Definition */
1734         unsigned int pd;        /* Power-Down Mode */
1735         unsigned int wr;        /* Write Recovery */
1736         unsigned int dll_res;   /* DLL Reset */
1737         unsigned int mode;      /* Normal=0 or Test=1 */
1738         unsigned int caslat = 0;/* CAS# latency */
1739         /* BT: Burst Type (0=Sequential, 1=Interleaved) */
1740         unsigned int bt;
1741         unsigned int bl;        /* BL: Burst Length */
1742
1743         dqs_en = !popts->dqs_config;
1744         rtt = fsl_ddr_get_rtt();
1745
1746         al = additive_latency;
1747
1748         esdmode = (0
1749                 | ((mrs & 0x3) << 14)
1750                 | ((outputs & 0x1) << 12)
1751                 | ((rdqs_en & 0x1) << 11)
1752                 | ((dqs_en & 0x1) << 10)
1753                 | ((ocd & 0x7) << 7)
1754                 | ((rtt & 0x2) << 5)   /* rtt field is split */
1755                 | ((al & 0x7) << 3)
1756                 | ((rtt & 0x1) << 2)   /* rtt field is split */
1757                 | ((ods & 0x1) << 1)
1758                 | ((dll_en & 0x1) << 0)
1759                 );
1760
1761         mr = 0;          /* FIXME: CHECKME */
1762
1763         /*
1764          * 0 = Fast Exit (Normal)
1765          * 1 = Slow Exit (Low Power)
1766          */
1767         pd = 0;
1768
1769 #if defined(CONFIG_SYS_FSL_DDR1)
1770         wr = 0;       /* Historical */
1771 #elif defined(CONFIG_SYS_FSL_DDR2)
1772         wr = picos_to_mclk(ctrl_num, common_dimm->twr_ps);
1773 #endif
1774         dll_res = 0;
1775         mode = 0;
1776
1777 #if defined(CONFIG_SYS_FSL_DDR1)
1778         if (1 <= cas_latency && cas_latency <= 4) {
1779                 unsigned char mode_caslat_table[4] = {
1780                         0x5,    /* 1.5 clocks */
1781                         0x2,    /* 2.0 clocks */
1782                         0x6,    /* 2.5 clocks */
1783                         0x3     /* 3.0 clocks */
1784                 };
1785                 caslat = mode_caslat_table[cas_latency - 1];
1786         } else {
1787                 printf("Warning: unknown cas_latency %d\n", cas_latency);
1788         }
1789 #elif defined(CONFIG_SYS_FSL_DDR2)
1790         caslat = cas_latency;
1791 #endif
1792         bt = 0;
1793
1794         switch (popts->burst_length) {
1795         case DDR_BL4:
1796                 bl = 2;
1797                 break;
1798         case DDR_BL8:
1799                 bl = 3;
1800                 break;
1801         default:
1802                 printf("Error: invalid burst length of %u specified. "
1803                         " Defaulting to 4 beats.\n",
1804                         popts->burst_length);
1805                 bl = 2;
1806                 break;
1807         }
1808
1809         sdmode = (0
1810                   | ((mr & 0x3) << 14)
1811                   | ((pd & 0x1) << 12)
1812                   | ((wr & 0x7) << 9)
1813                   | ((dll_res & 0x1) << 8)
1814                   | ((mode & 0x1) << 7)
1815                   | ((caslat & 0x7) << 4)
1816                   | ((bt & 0x1) << 3)
1817                   | ((bl & 0x7) << 0)
1818                   );
1819
1820         ddr->ddr_sdram_mode = (0
1821                                | ((esdmode & 0xFFFF) << 16)
1822                                | ((sdmode & 0xFFFF) << 0)
1823                                );
1824         debug("FSLDDR: ddr_sdram_mode = 0x%08x\n", ddr->ddr_sdram_mode);
1825 }
1826 #endif
1827
1828 /* DDR SDRAM Data Initialization (DDR_DATA_INIT) */
1829 static void set_ddr_data_init(fsl_ddr_cfg_regs_t *ddr)
1830 {
1831         unsigned int init_value;        /* Initialization value */
1832
1833 #ifdef CONFIG_MEM_INIT_VALUE
1834         init_value = CONFIG_MEM_INIT_VALUE;
1835 #else
1836         init_value = 0xDEADBEEF;
1837 #endif
1838         ddr->ddr_data_init = init_value;
1839 }
1840
1841 /*
1842  * DDR SDRAM Clock Control (DDR_SDRAM_CLK_CNTL)
1843  * The old controller on the 8540/60 doesn't have this register.
1844  * Hope it's OK to set it (to 0) anyway.
1845  */
1846 static void set_ddr_sdram_clk_cntl(fsl_ddr_cfg_regs_t *ddr,
1847                                          const memctl_options_t *popts)
1848 {
1849         unsigned int clk_adjust;        /* Clock adjust */
1850         unsigned int ss_en = 0;         /* Source synchronous enable */
1851
1852 #if defined(CONFIG_ARCH_MPC8541) || defined(CONFIG_ARCH_MPC8555)
1853         /* Per FSL Application Note: AN2805 */
1854         ss_en = 1;
1855 #endif
1856         if (fsl_ddr_get_version(0) >= 0x40701) {
1857                 /* clk_adjust in 5-bits on T-series and LS-series */
1858                 clk_adjust = (popts->clk_adjust & 0x1F) << 22;
1859         } else {
1860                 /* clk_adjust in 4-bits on earlier MPC85xx and P-series */
1861                 clk_adjust = (popts->clk_adjust & 0xF) << 23;
1862         }
1863
1864         ddr->ddr_sdram_clk_cntl = (0
1865                                    | ((ss_en & 0x1) << 31)
1866                                    | clk_adjust
1867                                    );
1868         debug("FSLDDR: clk_cntl = 0x%08x\n", ddr->ddr_sdram_clk_cntl);
1869 }
1870
1871 /* DDR Initialization Address (DDR_INIT_ADDR) */
1872 static void set_ddr_init_addr(fsl_ddr_cfg_regs_t *ddr)
1873 {
1874         unsigned int init_addr = 0;     /* Initialization address */
1875
1876         ddr->ddr_init_addr = init_addr;
1877 }
1878
1879 /* DDR Initialization Address (DDR_INIT_EXT_ADDR) */
1880 static void set_ddr_init_ext_addr(fsl_ddr_cfg_regs_t *ddr)
1881 {
1882         unsigned int uia = 0;   /* Use initialization address */
1883         unsigned int init_ext_addr = 0; /* Initialization address */
1884
1885         ddr->ddr_init_ext_addr = (0
1886                                   | ((uia & 0x1) << 31)
1887                                   | (init_ext_addr & 0xF)
1888                                   );
1889 }
1890
1891 /* DDR SDRAM Timing Configuration 4 (TIMING_CFG_4) */
1892 static void set_timing_cfg_4(fsl_ddr_cfg_regs_t *ddr,
1893                                 const memctl_options_t *popts)
1894 {
1895         unsigned int rwt = 0; /* Read-to-write turnaround for same CS */
1896         unsigned int wrt = 0; /* Write-to-read turnaround for same CS */
1897         unsigned int rrt = 0; /* Read-to-read turnaround for same CS */
1898         unsigned int wwt = 0; /* Write-to-write turnaround for same CS */
1899         unsigned int trwt_mclk = 0;     /* ext_rwt */
1900         unsigned int dll_lock = 0; /* DDR SDRAM DLL Lock Time */
1901
1902 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1903         if (popts->burst_length == DDR_BL8) {
1904                 /* We set BL/2 for fixed BL8 */
1905                 rrt = 0;        /* BL/2 clocks */
1906                 wwt = 0;        /* BL/2 clocks */
1907         } else {
1908                 /* We need to set BL/2 + 2 to BC4 and OTF */
1909                 rrt = 2;        /* BL/2 + 2 clocks */
1910                 wwt = 2;        /* BL/2 + 2 clocks */
1911         }
1912 #endif
1913 #ifdef CONFIG_SYS_FSL_DDR4
1914         dll_lock = 2;   /* tDLLK = 1024 clocks */
1915 #elif defined(CONFIG_SYS_FSL_DDR3)
1916         dll_lock = 1;   /* tDLLK = 512 clocks from spec */
1917 #endif
1918
1919         if (popts->trwt_override)
1920                 trwt_mclk = popts->trwt;
1921
1922         ddr->timing_cfg_4 = (0
1923                              | ((rwt & 0xf) << 28)
1924                              | ((wrt & 0xf) << 24)
1925                              | ((rrt & 0xf) << 20)
1926                              | ((wwt & 0xf) << 16)
1927                              | ((trwt_mclk & 0xc) << 12)
1928                              | (dll_lock & 0x3)
1929                              );
1930         debug("FSLDDR: timing_cfg_4 = 0x%08x\n", ddr->timing_cfg_4);
1931 }
1932
1933 /* DDR SDRAM Timing Configuration 5 (TIMING_CFG_5) */
1934 static void set_timing_cfg_5(fsl_ddr_cfg_regs_t *ddr, unsigned int cas_latency)
1935 {
1936         unsigned int rodt_on = 0;       /* Read to ODT on */
1937         unsigned int rodt_off = 0;      /* Read to ODT off */
1938         unsigned int wodt_on = 0;       /* Write to ODT on */
1939         unsigned int wodt_off = 0;      /* Write to ODT off */
1940
1941 #if defined(CONFIG_SYS_FSL_DDR3) || defined(CONFIG_SYS_FSL_DDR4)
1942         unsigned int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
1943                               ((ddr->timing_cfg_2 & 0x00040000) >> 14);
1944         /* rodt_on = timing_cfg_1[caslat] - timing_cfg_2[wrlat] + 1 */
1945         if (cas_latency >= wr_lat)
1946                 rodt_on = cas_latency - wr_lat + 1;
1947         rodt_off = 4;   /*  4 clocks */
1948         wodt_on = 1;    /*  1 clocks */
1949         wodt_off = 4;   /*  4 clocks */
1950 #endif
1951
1952         ddr->timing_cfg_5 = (0
1953                              | ((rodt_on & 0x1f) << 24)
1954                              | ((rodt_off & 0x7) << 20)
1955                              | ((wodt_on & 0x1f) << 12)
1956                              | ((wodt_off & 0x7) << 8)
1957                              );
1958         debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5);
1959 }
1960
1961 #ifdef CONFIG_SYS_FSL_DDR4
1962 static void set_timing_cfg_6(fsl_ddr_cfg_regs_t *ddr)
1963 {
1964         unsigned int hs_caslat = 0;
1965         unsigned int hs_wrlat = 0;
1966         unsigned int hs_wrrec = 0;
1967         unsigned int hs_clkadj = 0;
1968         unsigned int hs_wrlvl_start = 0;
1969
1970         ddr->timing_cfg_6 = (0
1971                              | ((hs_caslat & 0x1f) << 24)
1972                              | ((hs_wrlat & 0x1f) << 19)
1973                              | ((hs_wrrec & 0x1f) << 12)
1974                              | ((hs_clkadj & 0x1f) << 6)
1975                              | ((hs_wrlvl_start & 0x1f) << 0)
1976                             );
1977         debug("FSLDDR: timing_cfg_6 = 0x%08x\n", ddr->timing_cfg_6);
1978 }
1979
1980 static void set_timing_cfg_7(const unsigned int ctrl_num,
1981                              fsl_ddr_cfg_regs_t *ddr,
1982                              const memctl_options_t *popts,
1983                              const common_timing_params_t *common_dimm)
1984 {
1985         unsigned int txpr, tcksre, tcksrx;
1986         unsigned int cke_rst, cksre, cksrx, par_lat = 0, cs_to_cmd;
1987         const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num);
1988
1989         txpr = max(5U, picos_to_mclk(ctrl_num, common_dimm->trfc1_ps + 10000));
1990         tcksre = max(5U, picos_to_mclk(ctrl_num, 10000));
1991         tcksrx = max(5U, picos_to_mclk(ctrl_num, 10000));
1992
1993         if (ddr->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN &&
1994             CONFIG_FSL_SDRAM_TYPE == SDRAM_TYPE_DDR4) {
1995                 /* for DDR4 only */
1996                 par_lat = (ddr->ddr_sdram_rcw_2 & 0xf) + 1;
1997                 debug("PAR_LAT = %u for mclk_ps = %d\n", par_lat, mclk_ps);
1998         }
1999
2000         cs_to_cmd = 0;
2001
2002         if (txpr <= 200)
2003                 cke_rst = 0;
2004         else if (txpr <= 256)
2005                 cke_rst = 1;
2006         else if (txpr <= 512)
2007                 cke_rst = 2;
2008         else
2009                 cke_rst = 3;
2010
2011         if (tcksre <= 19)
2012                 cksre = tcksre - 5;
2013         else
2014                 cksre = 15;
2015
2016         if (tcksrx <= 19)
2017                 cksrx = tcksrx - 5;
2018         else
2019                 cksrx = 15;
2020
2021         ddr->timing_cfg_7 = (0
2022                              | ((cke_rst & 0x3) << 28)
2023                              | ((cksre & 0xf) << 24)
2024                              | ((cksrx & 0xf) << 20)
2025                              | ((par_lat & 0xf) << 16)
2026                              | ((cs_to_cmd & 0xf) << 4)
2027                             );
2028         debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7);
2029 }
2030
2031 static void set_timing_cfg_8(const unsigned int ctrl_num,
2032                              fsl_ddr_cfg_regs_t *ddr,
2033                              const memctl_options_t *popts,
2034                              const common_timing_params_t *common_dimm,
2035                              unsigned int cas_latency)
2036 {
2037         int rwt_bg, wrt_bg, rrt_bg, wwt_bg;
2038         unsigned int acttoact_bg, wrtord_bg, pre_all_rec;
2039         int tccdl = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps);
2040         int wr_lat = ((ddr->timing_cfg_2 & 0x00780000) >> 19) +
2041                       ((ddr->timing_cfg_2 & 0x00040000) >> 14);
2042
2043         rwt_bg = cas_latency + 2 + 4 - wr_lat;
2044         if (rwt_bg < tccdl)
2045                 rwt_bg = tccdl - rwt_bg;
2046         else
2047                 rwt_bg = 0;
2048
2049         wrt_bg = wr_lat + 4 + 1 - cas_latency;
2050         if (wrt_bg < tccdl)
2051                 wrt_bg = tccdl - wrt_bg;
2052         else
2053                 wrt_bg = 0;
2054
2055         if (popts->burst_length == DDR_BL8) {
2056                 rrt_bg = tccdl - 4;
2057                 wwt_bg = tccdl - 4;
2058         } else {
2059                 rrt_bg = tccdl - 2;
2060                 wwt_bg = tccdl - 2;
2061         }
2062
2063         acttoact_bg = picos_to_mclk(ctrl_num, common_dimm->trrdl_ps);
2064         wrtord_bg = max(4U, picos_to_mclk(ctrl_num, 7500));
2065         if (popts->otf_burst_chop_en)
2066                 wrtord_bg += 2;
2067
2068         pre_all_rec = 0;
2069
2070         ddr->timing_cfg_8 = (0
2071                              | ((rwt_bg & 0xf) << 28)
2072                              | ((wrt_bg & 0xf) << 24)
2073                              | ((rrt_bg & 0xf) << 20)
2074                              | ((wwt_bg & 0xf) << 16)
2075                              | ((acttoact_bg & 0xf) << 12)
2076                              | ((wrtord_bg & 0xf) << 8)
2077                              | ((pre_all_rec & 0x1f) << 0)
2078                             );
2079
2080         debug("FSLDDR: timing_cfg_8 = 0x%08x\n", ddr->timing_cfg_8);
2081 }
2082
2083 static void set_timing_cfg_9(const unsigned int ctrl_num,
2084                              fsl_ddr_cfg_regs_t *ddr,
2085                              const memctl_options_t *popts,
2086                              const common_timing_params_t *common_dimm)
2087 {
2088         unsigned int refrec_cid_mclk = 0;
2089         unsigned int acttoact_cid_mclk = 0;
2090
2091         if (popts->package_3ds) {
2092                 refrec_cid_mclk =
2093                         picos_to_mclk(ctrl_num, common_dimm->trfc_slr_ps);
2094                 acttoact_cid_mclk = 4U; /* tRRDS_slr */
2095         }
2096
2097         ddr->timing_cfg_9 = (refrec_cid_mclk & 0x3ff) << 16     |
2098                             (acttoact_cid_mclk & 0xf) << 8;
2099
2100         debug("FSLDDR: timing_cfg_9 = 0x%08x\n", ddr->timing_cfg_9);
2101 }
2102
2103 /* This function needs to be called after set_ddr_sdram_cfg() is called */
2104 static void set_ddr_dq_mapping(fsl_ddr_cfg_regs_t *ddr,
2105                                const dimm_params_t *dimm_params)
2106 {
2107         unsigned int acc_ecc_en = (ddr->ddr_sdram_cfg >> 2) & 0x1;
2108         int i;
2109
2110         for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
2111                 if (dimm_params[i].n_ranks)
2112                         break;
2113         }
2114         if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) {
2115                 puts("DDR error: no DIMM found!\n");
2116                 return;
2117         }
2118
2119         ddr->dq_map_0 = ((dimm_params[i].dq_mapping[0] & 0x3F) << 26) |
2120                         ((dimm_params[i].dq_mapping[1] & 0x3F) << 20) |
2121                         ((dimm_params[i].dq_mapping[2] & 0x3F) << 14) |
2122                         ((dimm_params[i].dq_mapping[3] & 0x3F) << 8) |
2123                         ((dimm_params[i].dq_mapping[4] & 0x3F) << 2);
2124
2125         ddr->dq_map_1 = ((dimm_params[i].dq_mapping[5] & 0x3F) << 26) |
2126                         ((dimm_params[i].dq_mapping[6] & 0x3F) << 20) |
2127                         ((dimm_params[i].dq_mapping[7] & 0x3F) << 14) |
2128                         ((dimm_params[i].dq_mapping[10] & 0x3F) << 8) |
2129                         ((dimm_params[i].dq_mapping[11] & 0x3F) << 2);
2130
2131         ddr->dq_map_2 = ((dimm_params[i].dq_mapping[12] & 0x3F) << 26) |
2132                         ((dimm_params[i].dq_mapping[13] & 0x3F) << 20) |
2133                         ((dimm_params[i].dq_mapping[14] & 0x3F) << 14) |
2134                         ((dimm_params[i].dq_mapping[15] & 0x3F) << 8) |
2135                         ((dimm_params[i].dq_mapping[16] & 0x3F) << 2);
2136
2137         /* dq_map for ECC[4:7] is set to 0 if accumulated ECC is enabled */
2138         ddr->dq_map_3 = ((dimm_params[i].dq_mapping[17] & 0x3F) << 26) |
2139                         ((dimm_params[i].dq_mapping[8] & 0x3F) << 20) |
2140                         (acc_ecc_en ? 0 :
2141                          (dimm_params[i].dq_mapping[9] & 0x3F) << 14) |
2142                         dimm_params[i].dq_mapping_ors;
2143
2144         debug("FSLDDR: dq_map_0 = 0x%08x\n", ddr->dq_map_0);
2145         debug("FSLDDR: dq_map_1 = 0x%08x\n", ddr->dq_map_1);
2146         debug("FSLDDR: dq_map_2 = 0x%08x\n", ddr->dq_map_2);
2147         debug("FSLDDR: dq_map_3 = 0x%08x\n", ddr->dq_map_3);
2148 }
2149 static void set_ddr_sdram_cfg_3(fsl_ddr_cfg_regs_t *ddr,
2150                                const memctl_options_t *popts)
2151 {
2152         int rd_pre;
2153
2154         rd_pre = popts->quad_rank_present ? 1 : 0;
2155
2156         ddr->ddr_sdram_cfg_3 = (rd_pre & 0x1) << 16;
2157         /* Disable MRS on parity error for RDIMMs */
2158         ddr->ddr_sdram_cfg_3 |= popts->registered_dimm_en ? 1 : 0;
2159
2160         if (popts->package_3ds) {       /* only 2,4,8 are supported */
2161                 if ((popts->package_3ds + 1) & 0x1) {
2162                         printf("Error: Unsupported 3DS DIMM with %d die\n",
2163                                popts->package_3ds + 1);
2164                 } else {
2165                         ddr->ddr_sdram_cfg_3 |= ((popts->package_3ds + 1) >> 1)
2166                                                 << 4;
2167                 }
2168         }
2169
2170         debug("FSLDDR: ddr_sdram_cfg_3 = 0x%08x\n", ddr->ddr_sdram_cfg_3);
2171 }
2172 #endif  /* CONFIG_SYS_FSL_DDR4 */
2173
2174 /* DDR ZQ Calibration Control (DDR_ZQ_CNTL) */
2175 static void set_ddr_zq_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int zq_en)
2176 {
2177         unsigned int zqinit = 0;/* POR ZQ Calibration Time (tZQinit) */
2178         /* Normal Operation Full Calibration Time (tZQoper) */
2179         unsigned int zqoper = 0;
2180         /* Normal Operation Short Calibration Time (tZQCS) */
2181         unsigned int zqcs = 0;
2182 #ifdef CONFIG_SYS_FSL_DDR4
2183         unsigned int zqcs_init;
2184 #endif
2185
2186         if (zq_en) {
2187 #ifdef CONFIG_SYS_FSL_DDR4
2188                 zqinit = 10;    /* 1024 clocks */
2189                 zqoper = 9;     /* 512 clocks */
2190                 zqcs = 7;       /* 128 clocks */
2191                 zqcs_init = 5;  /* 1024 refresh sequences */
2192 #else
2193                 zqinit = 9;     /* 512 clocks */
2194                 zqoper = 8;     /* 256 clocks */
2195                 zqcs = 6;       /* 64 clocks */
2196 #endif
2197         }
2198
2199         ddr->ddr_zq_cntl = (0
2200                             | ((zq_en & 0x1) << 31)
2201                             | ((zqinit & 0xF) << 24)
2202                             | ((zqoper & 0xF) << 16)
2203                             | ((zqcs & 0xF) << 8)
2204 #ifdef CONFIG_SYS_FSL_DDR4
2205                             | ((zqcs_init & 0xF) << 0)
2206 #endif
2207                             );
2208         debug("FSLDDR: zq_cntl = 0x%08x\n", ddr->ddr_zq_cntl);
2209 }
2210
2211 /* DDR Write Leveling Control (DDR_WRLVL_CNTL) */
2212 static void set_ddr_wrlvl_cntl(fsl_ddr_cfg_regs_t *ddr, unsigned int wrlvl_en,
2213                                 const memctl_options_t *popts)
2214 {
2215         /*
2216          * First DQS pulse rising edge after margining mode
2217          * is programmed (tWL_MRD)
2218          */
2219         unsigned int wrlvl_mrd = 0;
2220         /* ODT delay after margining mode is programmed (tWL_ODTEN) */
2221         unsigned int wrlvl_odten = 0;
2222         /* DQS/DQS_ delay after margining mode is programmed (tWL_DQSEN) */
2223         unsigned int wrlvl_dqsen = 0;
2224         /* WRLVL_SMPL: Write leveling sample time */
2225         unsigned int wrlvl_smpl = 0;
2226         /* WRLVL_WLR: Write leveling repeition time */
2227         unsigned int wrlvl_wlr = 0;
2228         /* WRLVL_START: Write leveling start time */
2229         unsigned int wrlvl_start = 0;
2230
2231         /* suggest enable write leveling for DDR3 due to fly-by topology */
2232         if (wrlvl_en) {
2233                 /* tWL_MRD min = 40 nCK, we set it 64 */
2234                 wrlvl_mrd = 0x6;
2235                 /* tWL_ODTEN 128 */
2236                 wrlvl_odten = 0x7;
2237                 /* tWL_DQSEN min = 25 nCK, we set it 32 */
2238                 wrlvl_dqsen = 0x5;
2239                 /*
2240                  * Write leveling sample time at least need 6 clocks
2241                  * higher than tWLO to allow enough time for progagation
2242                  * delay and sampling the prime data bits.
2243                  */
2244                 wrlvl_smpl = 0xf;
2245                 /*
2246                  * Write leveling repetition time
2247                  * at least tWLO + 6 clocks clocks
2248                  * we set it 64
2249                  */
2250                 wrlvl_wlr = 0x6;
2251                 /*
2252                  * Write leveling start time
2253                  * The value use for the DQS_ADJUST for the first sample
2254                  * when write leveling is enabled. It probably needs to be
2255                  * overridden per platform.
2256                  */
2257                 wrlvl_start = 0x8;
2258                 /*
2259                  * Override the write leveling sample and start time
2260                  * according to specific board
2261                  */
2262                 if (popts->wrlvl_override) {
2263                         wrlvl_smpl = popts->wrlvl_sample;
2264                         wrlvl_start = popts->wrlvl_start;
2265                 }
2266         }
2267
2268         ddr->ddr_wrlvl_cntl = (0
2269                                | ((wrlvl_en & 0x1) << 31)
2270                                | ((wrlvl_mrd & 0x7) << 24)
2271                                | ((wrlvl_odten & 0x7) << 20)
2272                                | ((wrlvl_dqsen & 0x7) << 16)
2273                                | ((wrlvl_smpl & 0xf) << 12)
2274                                | ((wrlvl_wlr & 0x7) << 8)
2275                                | ((wrlvl_start & 0x1F) << 0)
2276                                );
2277         debug("FSLDDR: wrlvl_cntl = 0x%08x\n", ddr->ddr_wrlvl_cntl);
2278         ddr->ddr_wrlvl_cntl_2 = popts->wrlvl_ctl_2;
2279         debug("FSLDDR: wrlvl_cntl_2 = 0x%08x\n", ddr->ddr_wrlvl_cntl_2);
2280         ddr->ddr_wrlvl_cntl_3 = popts->wrlvl_ctl_3;
2281         debug("FSLDDR: wrlvl_cntl_3 = 0x%08x\n", ddr->ddr_wrlvl_cntl_3);
2282
2283 }
2284
2285 /* DDR Self Refresh Counter (DDR_SR_CNTR) */
2286 static void set_ddr_sr_cntr(fsl_ddr_cfg_regs_t *ddr, unsigned int sr_it)
2287 {
2288         /* Self Refresh Idle Threshold */
2289         ddr->ddr_sr_cntr = (sr_it & 0xF) << 16;
2290 }
2291
2292 static void set_ddr_eor(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2293 {
2294         if (popts->addr_hash) {
2295                 ddr->ddr_eor = 0x40000000;      /* address hash enable */
2296                 puts("Address hashing enabled.\n");
2297         }
2298 }
2299
2300 static void set_ddr_cdr1(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2301 {
2302         ddr->ddr_cdr1 = popts->ddr_cdr1;
2303         debug("FSLDDR: ddr_cdr1 = 0x%08x\n", ddr->ddr_cdr1);
2304 }
2305
2306 static void set_ddr_cdr2(fsl_ddr_cfg_regs_t *ddr, const memctl_options_t *popts)
2307 {
2308         ddr->ddr_cdr2 = popts->ddr_cdr2;
2309         debug("FSLDDR: ddr_cdr2 = 0x%08x\n", ddr->ddr_cdr2);
2310 }
2311
2312 unsigned int
2313 check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr)
2314 {
2315         unsigned int res = 0;
2316
2317         /*
2318          * Check that DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] are
2319          * not set at the same time.
2320          */
2321         if (ddr->ddr_sdram_cfg & 0x10000000
2322             && ddr->ddr_sdram_cfg & 0x00008000) {
2323                 printf("Error: DDR_SDRAM_CFG[RD_EN] and DDR_SDRAM_CFG[2T_EN] "
2324                                 " should not be set at the same time.\n");
2325                 res++;
2326         }
2327
2328         return res;
2329 }
2330
2331 unsigned int
2332 compute_fsl_memctl_config_regs(const unsigned int ctrl_num,
2333                                const memctl_options_t *popts,
2334                                fsl_ddr_cfg_regs_t *ddr,
2335                                const common_timing_params_t *common_dimm,
2336                                const dimm_params_t *dimm_params,
2337                                unsigned int dbw_cap_adj,
2338                                unsigned int size_only)
2339 {
2340         unsigned int i;
2341         unsigned int cas_latency;
2342         unsigned int additive_latency;
2343         unsigned int sr_it;
2344         unsigned int zq_en;
2345         unsigned int wrlvl_en;
2346         unsigned int ip_rev = 0;
2347         unsigned int unq_mrs_en = 0;
2348         int cs_en = 1;
2349 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
2350         unsigned int ddr_freq;
2351 #endif
2352 #if (defined(CONFIG_SYS_FSL_ERRATUM_A008378) && \
2353         defined(CONFIG_SYS_FSL_DDRC_GEN4)) || \
2354         defined(CONFIG_SYS_FSL_ERRATUM_A009942)
2355         struct ccsr_ddr __iomem *ddrc;
2356
2357         switch (ctrl_num) {
2358         case 0:
2359                 ddrc = (void *)CONFIG_SYS_FSL_DDR_ADDR;
2360                 break;
2361 #if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1)
2362         case 1:
2363                 ddrc = (void *)CONFIG_SYS_FSL_DDR2_ADDR;
2364                 break;
2365 #endif
2366 #if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2)
2367         case 2:
2368                 ddrc = (void *)CONFIG_SYS_FSL_DDR3_ADDR;
2369                 break;
2370 #endif
2371 #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3)
2372         case 3:
2373                 ddrc = (void *)CONFIG_SYS_FSL_DDR4_ADDR;
2374                 break;
2375 #endif
2376         default:
2377                 printf("%s unexpected ctrl_num = %u\n", __func__, ctrl_num);
2378                 return 1;
2379         }
2380 #endif
2381
2382         memset(ddr, 0, sizeof(fsl_ddr_cfg_regs_t));
2383
2384         if (common_dimm == NULL) {
2385                 printf("Error: subset DIMM params struct null pointer\n");
2386                 return 1;
2387         }
2388
2389         /*
2390          * Process overrides first.
2391          *
2392          * FIXME: somehow add dereated caslat to this
2393          */
2394         cas_latency = (popts->cas_latency_override)
2395                 ? popts->cas_latency_override_value
2396                 : common_dimm->lowest_common_spd_caslat;
2397
2398         additive_latency = (popts->additive_latency_override)
2399                 ? popts->additive_latency_override_value
2400                 : common_dimm->additive_latency;
2401
2402         sr_it = (popts->auto_self_refresh_en)
2403                 ? popts->sr_it
2404                 : 0;
2405         /* ZQ calibration */
2406         zq_en = (popts->zq_en) ? 1 : 0;
2407         /* write leveling */
2408         wrlvl_en = (popts->wrlvl_en) ? 1 : 0;
2409
2410         /* Chip Select Memory Bounds (CSn_BNDS) */
2411         for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
2412                 unsigned long long ea, sa;
2413                 unsigned int cs_per_dimm
2414                         = CONFIG_CHIP_SELECTS_PER_CTRL / CONFIG_DIMM_SLOTS_PER_CTLR;
2415                 unsigned int dimm_number
2416                         = i / cs_per_dimm;
2417                 unsigned long long rank_density
2418                         = dimm_params[dimm_number].rank_density >> dbw_cap_adj;
2419
2420                 if (dimm_params[dimm_number].n_ranks == 0) {
2421                         debug("Skipping setup of CS%u "
2422                                 "because n_ranks on DIMM %u is 0\n", i, dimm_number);
2423                         continue;
2424                 }
2425                 if (popts->memctl_interleaving) {
2426                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
2427                         case FSL_DDR_CS0_CS1_CS2_CS3:
2428                                 break;
2429                         case FSL_DDR_CS0_CS1:
2430                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
2431                                 if (i > 1)
2432                                         cs_en = 0;
2433                                 break;
2434                         case FSL_DDR_CS2_CS3:
2435                         default:
2436                                 if (i > 0)
2437                                         cs_en = 0;
2438                                 break;
2439                         }
2440                         sa = common_dimm->base_address;
2441                         ea = sa + common_dimm->total_mem - 1;
2442                 } else if (!popts->memctl_interleaving) {
2443                         /*
2444                          * If memory interleaving between controllers is NOT
2445                          * enabled, the starting address for each memory
2446                          * controller is distinct.  However, because rank
2447                          * interleaving is enabled, the starting and ending
2448                          * addresses of the total memory on that memory
2449                          * controller needs to be programmed into its
2450                          * respective CS0_BNDS.
2451                          */
2452                         switch (popts->ba_intlv_ctl & FSL_DDR_CS0_CS1_CS2_CS3) {
2453                         case FSL_DDR_CS0_CS1_CS2_CS3:
2454                                 sa = common_dimm->base_address;
2455                                 ea = sa + common_dimm->total_mem - 1;
2456                                 break;
2457                         case FSL_DDR_CS0_CS1_AND_CS2_CS3:
2458                                 if ((i >= 2) && (dimm_number == 0)) {
2459                                         sa = dimm_params[dimm_number].base_address +
2460                                               2 * rank_density;
2461                                         ea = sa + 2 * rank_density - 1;
2462                                 } else {
2463                                         sa = dimm_params[dimm_number].base_address;
2464                                         ea = sa + 2 * rank_density - 1;
2465                                 }
2466                                 break;
2467                         case FSL_DDR_CS0_CS1:
2468                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2469                                         sa = dimm_params[dimm_number].base_address;
2470                                         ea = sa + rank_density - 1;
2471                                         if (i != 1)
2472                                                 sa += (i % cs_per_dimm) * rank_density;
2473                                         ea += (i % cs_per_dimm) * rank_density;
2474                                 } else {
2475                                         sa = 0;
2476                                         ea = 0;
2477                                 }
2478                                 if (i == 0)
2479                                         ea += rank_density;
2480                                 break;
2481                         case FSL_DDR_CS2_CS3:
2482                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2483                                         sa = dimm_params[dimm_number].base_address;
2484                                         ea = sa + rank_density - 1;
2485                                         if (i != 3)
2486                                                 sa += (i % cs_per_dimm) * rank_density;
2487                                         ea += (i % cs_per_dimm) * rank_density;
2488                                 } else {
2489                                         sa = 0;
2490                                         ea = 0;
2491                                 }
2492                                 if (i == 2)
2493                                         ea += (rank_density >> dbw_cap_adj);
2494                                 break;
2495                         default:  /* No bank(chip-select) interleaving */
2496                                 sa = dimm_params[dimm_number].base_address;
2497                                 ea = sa + rank_density - 1;
2498                                 if (dimm_params[dimm_number].n_ranks > (i % cs_per_dimm)) {
2499                                         sa += (i % cs_per_dimm) * rank_density;
2500                                         ea += (i % cs_per_dimm) * rank_density;
2501                                 } else {
2502                                         sa = 0;
2503                                         ea = 0;
2504                                 }
2505                                 break;
2506                         }
2507                 }
2508
2509                 sa >>= 24;
2510                 ea >>= 24;
2511
2512                 if (cs_en) {
2513                         ddr->cs[i].bnds = (0
2514                                 | ((sa & 0xffff) << 16) /* starting address */
2515                                 | ((ea & 0xffff) << 0)  /* ending address */
2516                                 );
2517                 } else {
2518                         /* setting bnds to 0xffffffff for inactive CS */
2519                         ddr->cs[i].bnds = 0xffffffff;
2520                 }
2521
2522                 debug("FSLDDR: cs[%d]_bnds = 0x%08x\n", i, ddr->cs[i].bnds);
2523                 set_csn_config(dimm_number, i, ddr, popts, dimm_params);
2524                 set_csn_config_2(i, ddr);
2525         }
2526
2527         /*
2528          * In the case we only need to compute the ddr sdram size, we only need
2529          * to set csn registers, so return from here.
2530          */
2531         if (size_only)
2532                 return 0;
2533
2534         set_ddr_eor(ddr, popts);
2535
2536 #if !defined(CONFIG_SYS_FSL_DDR1)
2537         set_timing_cfg_0(ctrl_num, ddr, popts, dimm_params);
2538 #endif
2539
2540         set_timing_cfg_3(ctrl_num, ddr, popts, common_dimm, cas_latency,
2541                          additive_latency);
2542         set_timing_cfg_1(ctrl_num, ddr, popts, common_dimm, cas_latency);
2543         set_timing_cfg_2(ctrl_num, ddr, popts, common_dimm,
2544                          cas_latency, additive_latency);
2545
2546         set_ddr_cdr1(ddr, popts);
2547         set_ddr_cdr2(ddr, popts);
2548         set_ddr_sdram_cfg(ddr, popts, common_dimm);
2549         ip_rev = fsl_ddr_get_version(ctrl_num);
2550         if (ip_rev > 0x40400)
2551                 unq_mrs_en = 1;
2552
2553         if ((ip_rev > 0x40700) && (popts->cswl_override != 0))
2554                 ddr->debug[18] = popts->cswl_override;
2555
2556         set_ddr_sdram_cfg_2(ctrl_num, ddr, popts, unq_mrs_en);
2557         set_ddr_sdram_mode(ctrl_num, ddr, popts, common_dimm,
2558                            cas_latency, additive_latency, unq_mrs_en);
2559         set_ddr_sdram_mode_2(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
2560 #ifdef CONFIG_SYS_FSL_DDR4
2561         set_ddr_sdram_mode_9(ddr, popts, common_dimm, unq_mrs_en);
2562         set_ddr_sdram_mode_10(ctrl_num, ddr, popts, common_dimm, unq_mrs_en);
2563 #endif
2564         set_ddr_sdram_interval(ctrl_num, ddr, popts, common_dimm);
2565         set_ddr_data_init(ddr);
2566         set_ddr_sdram_clk_cntl(ddr, popts);
2567         set_ddr_init_addr(ddr);
2568         set_ddr_init_ext_addr(ddr);
2569         set_timing_cfg_4(ddr, popts);
2570         set_timing_cfg_5(ddr, cas_latency);
2571 #ifdef CONFIG_SYS_FSL_DDR4
2572         set_ddr_sdram_cfg_3(ddr, popts);
2573         set_timing_cfg_6(ddr);
2574         set_timing_cfg_7(ctrl_num, ddr, popts, common_dimm);
2575         set_timing_cfg_8(ctrl_num, ddr, popts, common_dimm, cas_latency);
2576         set_timing_cfg_9(ctrl_num, ddr, popts, common_dimm);
2577         set_ddr_dq_mapping(ddr, dimm_params);
2578 #endif
2579
2580         set_ddr_zq_cntl(ddr, zq_en);
2581         set_ddr_wrlvl_cntl(ddr, wrlvl_en, popts);
2582
2583         set_ddr_sr_cntr(ddr, sr_it);
2584
2585         set_ddr_sdram_rcw(ddr, popts, common_dimm);
2586
2587 #ifdef CONFIG_SYS_FSL_DDR_EMU
2588         /* disble DDR training for emulator */
2589         ddr->debug[2] = 0x00000400;
2590         ddr->debug[4] = 0xff800800;
2591         ddr->debug[5] = 0x08000800;
2592         ddr->debug[6] = 0x08000800;
2593         ddr->debug[7] = 0x08000800;
2594         ddr->debug[8] = 0x08000800;
2595 #endif
2596 #ifdef CONFIG_SYS_FSL_ERRATUM_A004508
2597         if ((ip_rev >= 0x40000) && (ip_rev < 0x40400))
2598                 ddr->debug[2] |= 0x00000200;    /* set bit 22 */
2599 #endif
2600
2601 #if defined(CONFIG_SYS_FSL_ERRATUM_A008378) && defined(CONFIG_SYS_FSL_DDRC_GEN4)
2602         /* Erratum applies when accumulated ECC is used, or DBI is enabled */
2603 #define IS_ACC_ECC_EN(v) ((v) & 0x4)
2604 #define IS_DBI(v) ((((v) >> 12) & 0x3) == 0x2)
2605         if (has_erratum_a008378()) {
2606                 if (IS_ACC_ECC_EN(ddr->ddr_sdram_cfg) ||
2607                     IS_DBI(ddr->ddr_sdram_cfg_3)) {
2608                         ddr->debug[28] = ddr_in32(&ddrc->debug[28]);
2609                         ddr->debug[28] |= (0x9 << 20);
2610                 }
2611         }
2612 #endif
2613
2614 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
2615         ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
2616         ddr->debug[28] |= ddr_in32(&ddrc->debug[28]);
2617         ddr->debug[28] &= 0xff0fff00;
2618         if (ddr_freq <= 1333)
2619                 ddr->debug[28] |= 0x0080006a;
2620         else if (ddr_freq <= 1600)
2621                 ddr->debug[28] |= 0x0070006f;
2622         else if (ddr_freq <= 1867)
2623                 ddr->debug[28] |= 0x00700076;
2624         else if (ddr_freq <= 2133)
2625                 ddr->debug[28] |= 0x0060007b;
2626         if (popts->cpo_sample)
2627                 ddr->debug[28] = (ddr->debug[28] & 0xffffff00) |
2628                                   popts->cpo_sample;
2629 #endif
2630
2631         return check_fsl_memctl_config_regs(ddr);
2632 }
2633
2634 #ifdef CONFIG_SYS_FSL_ERRATUM_A009942
2635 /*
2636  * This additional workaround of A009942 checks the condition to determine if
2637  * the CPO value set by the existing A009942 workaround needs to be updated.
2638  * If need, print a warning to prompt user reconfigure DDR debug_29[24:31] with
2639  * expected optimal value, the optimal value is highly board dependent.
2640  */
2641 void erratum_a009942_check_cpo(void)
2642 {
2643         struct ccsr_ddr __iomem *ddr =
2644                 (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR);
2645         u32 cpo, cpo_e, cpo_o, cpo_target, cpo_optimal;
2646         u32 cpo_min = ddr_in32(&ddr->debug[9]) >> 24;
2647         u32 cpo_max = cpo_min;
2648         u32 sdram_cfg, i, tmp, lanes, ddr_type;
2649         bool update_cpo = false, has_ecc = false;
2650
2651         sdram_cfg = ddr_in32(&ddr->sdram_cfg);
2652         if (sdram_cfg & SDRAM_CFG_32_BE)
2653                 lanes = 4;
2654         else if (sdram_cfg & SDRAM_CFG_16_BE)
2655                 lanes = 2;
2656         else
2657                 lanes = 8;
2658
2659         if (sdram_cfg & SDRAM_CFG_ECC_EN)
2660                 has_ecc = true;
2661
2662         /* determine the maximum and minimum CPO values */
2663         for (i = 9; i < 9 + lanes / 2; i++) {
2664                 cpo = ddr_in32(&ddr->debug[i]);
2665                 cpo_e = cpo >> 24;
2666                 cpo_o = (cpo >> 8) & 0xff;
2667                 tmp = min(cpo_e, cpo_o);
2668                 if (tmp < cpo_min)
2669                         cpo_min = tmp;
2670                 tmp = max(cpo_e, cpo_o);
2671                 if (tmp > cpo_max)
2672                         cpo_max = tmp;
2673         }
2674
2675         if (has_ecc) {
2676                 cpo = ddr_in32(&ddr->debug[13]);
2677                 cpo = cpo >> 24;
2678                 if (cpo < cpo_min)
2679                         cpo_min = cpo;
2680                 if (cpo > cpo_max)
2681                         cpo_max = cpo;
2682         }
2683
2684         cpo_target = ddr_in32(&ddr->debug[28]) & 0xff;
2685         cpo_optimal = ((cpo_max + cpo_min) >> 1) + 0x27;
2686         debug("cpo_optimal = 0x%x, cpo_target = 0x%x\n", cpo_optimal,
2687               cpo_target);
2688         debug("cpo_max = 0x%x, cpo_min = 0x%x\n", cpo_max, cpo_min);
2689
2690         ddr_type = (sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
2691                     SDRAM_CFG_SDRAM_TYPE_SHIFT;
2692         if (ddr_type == SDRAM_TYPE_DDR4)
2693                 update_cpo = (cpo_min + 0x3b) < cpo_target ? true : false;
2694         else if (ddr_type == SDRAM_TYPE_DDR3)
2695                 update_cpo = (cpo_min + 0x3f) < cpo_target ? true : false;
2696
2697         if (update_cpo) {
2698                 printf("WARN: pls set popts->cpo_sample = 0x%x ", cpo_optimal);
2699                 printf("in <board>/ddr.c to optimize cpo\n");
2700         }
2701 }
2702 #endif