git.sur5r.net Git - u-boot/blob - drivers/ddr/fsl/main.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright 2008-2014 Freescale Semiconductor, Inc.
   4  */
   5
   6 /*
   7  * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
   8  * Based on code from spd_sdram.c
   9  * Author: James Yang [at freescale.com]
  10  */
  11
  12 #include <common.h>
  13 #include <i2c.h>
  14 #include <fsl_ddr_sdram.h>
  15 #include <fsl_ddr.h>
  16
  17 /*
  18  * CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view
  19  * of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for
  20  * all Power SoCs. But it could be different for ARM SoCs. For example,
  21  * fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of
  22  * 0x00_8000_0000 ~ 0x00_ffff_ffff
  23  * 0x80_8000_0000 ~ 0xff_ffff_ffff
  24  */
  25 #ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY
  26 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE
  27 #endif
  28
  29 #ifdef CONFIG_PPC
  30 #include <asm/fsl_law.h>
  31
  32 void fsl_ddr_set_lawbar(
  33                 const common_timing_params_t *memctl_common_params,
  34                 unsigned int memctl_interleaved,
  35                 unsigned int ctrl_num);
  36 #endif
  37
  38 void fsl_ddr_set_intl3r(const unsigned int granule_size);
  39 #if defined(SPD_EEPROM_ADDRESS) || \
  40     defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
  41     defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
  42 #if (CONFIG_SYS_NUM_DDR_CTLRS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  43 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  44         [0][0] = SPD_EEPROM_ADDRESS,
  45 };
  46 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  47 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  48         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  49         [0][1] = SPD_EEPROM_ADDRESS2,   /* controller 1 */
  50 };
  51 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  52 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  53         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  54         [1][0] = SPD_EEPROM_ADDRESS2,   /* controller 2 */
  55 };
  56 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  57 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  58         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  59         [0][1] = SPD_EEPROM_ADDRESS2,   /* controller 1 */
  60         [1][0] = SPD_EEPROM_ADDRESS3,   /* controller 2 */
  61         [1][1] = SPD_EEPROM_ADDRESS4,   /* controller 2 */
  62 };
  63 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  64 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  65         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  66         [1][0] = SPD_EEPROM_ADDRESS2,   /* controller 2 */
  67         [2][0] = SPD_EEPROM_ADDRESS3,   /* controller 3 */
  68 };
  69 #elif (CONFIG_SYS_NUM_DDR_CTLRS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  70 u8 spd_i2c_addr[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  71         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  72         [0][1] = SPD_EEPROM_ADDRESS2,   /* controller 1 */
  73         [1][0] = SPD_EEPROM_ADDRESS3,   /* controller 2 */
  74         [1][1] = SPD_EEPROM_ADDRESS4,   /* controller 2 */
  75         [2][0] = SPD_EEPROM_ADDRESS5,   /* controller 3 */
  76         [2][1] = SPD_EEPROM_ADDRESS6,   /* controller 3 */
  77 };
  78
  79 #endif
  80
  81 #define SPD_SPA0_ADDRESS        0x36
  82 #define SPD_SPA1_ADDRESS        0x37
  83
  84 static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
  85 {
  86         int ret;
  87 #ifdef CONFIG_SYS_FSL_DDR4
  88         uint8_t dummy = 0;
  89 #endif
  90
  91         i2c_set_bus_num(CONFIG_SYS_SPD_BUS_NUM);
  92
  93 #ifdef CONFIG_SYS_FSL_DDR4
  94         /*
  95          * DDR4 SPD has 384 to 512 bytes
  96          * To access the lower 256 bytes, we need to set EE page address to 0
  97          * To access the upper 256 bytes, we need to set EE page address to 1
  98          * See Jedec standar No. 21-C for detail
  99          */
 100         i2c_write(SPD_SPA0_ADDRESS, 0, 1, &dummy, 1);
 101         ret = i2c_read(i2c_address, 0, 1, (uchar *)spd, 256);
 102         if (!ret) {
 103                 i2c_write(SPD_SPA1_ADDRESS, 0, 1, &dummy, 1);
 104                 ret = i2c_read(i2c_address, 0, 1,
 105                                (uchar *)((ulong)spd + 256),
 106                                min(256,
 107                                    (int)sizeof(generic_spd_eeprom_t) - 256));
 108         }
 109 #else
 110         ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
 111                                 sizeof(generic_spd_eeprom_t));
 112 #endif
 113
 114         if (ret) {
 115                 if (i2c_address ==
 116 #ifdef SPD_EEPROM_ADDRESS
 117                                 SPD_EEPROM_ADDRESS
 118 #elif defined(SPD_EEPROM_ADDRESS1)
 119                                 SPD_EEPROM_ADDRESS1
 120 #endif
 121                                 ) {
 122                         printf("DDR: failed to read SPD from address %u\n",
 123                                 i2c_address);
 124                 } else {
 125                         debug("DDR: failed to read SPD from address %u\n",
 126                                 i2c_address);
 127                 }
 128                 memset(spd, 0, sizeof(generic_spd_eeprom_t));
 129         }
 130 }
 131
 132 __attribute__((weak, alias("__get_spd")))
 133 void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address);
 134
 135 /* This function allows boards to update SPD address */
 136 __weak void update_spd_address(unsigned int ctrl_num,
 137                                unsigned int slot,
 138                                unsigned int *addr)
 139 {
 140 }
 141
 142 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
 143                       unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl)
 144 {
 145         unsigned int i;
 146         unsigned int i2c_address = 0;
 147
 148         if (ctrl_num >= CONFIG_SYS_NUM_DDR_CTLRS) {
 149                 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
 150                 return;
 151         }
 152
 153         for (i = 0; i < dimm_slots_per_ctrl; i++) {
 154                 i2c_address = spd_i2c_addr[ctrl_num][i];
 155                 update_spd_address(ctrl_num, i, &i2c_address);
 156                 get_spd(&(ctrl_dimms_spd[i]), i2c_address);
 157         }
 158 }
 159 #else
 160 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
 161                       unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl)
 162 {
 163 }
 164 #endif /* SPD_EEPROM_ADDRESSx */
 165
 166 /*
 167  * ASSUMPTIONS:
 168  *    - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller
 169  *    - Same memory data bus width on all controllers
 170  *
 171  * NOTES:
 172  *
 173  * The memory controller and associated documentation use confusing
 174  * terminology when referring to the orgranization of DRAM.
 175  *
 176  * Here is a terminology translation table:
 177  *
 178  * memory controller/documention  |industry   |this code  |signals
 179  * -------------------------------|-----------|-----------|-----------------
 180  * physical bank/bank             |rank       |rank       |chip select (CS)
 181  * logical bank/sub-bank          |bank       |bank       |bank address (BA)
 182  * page/row                       |row        |page       |row address
 183  * ???                            |column     |column     |column address
 184  *
 185  * The naming confusion is further exacerbated by the descriptions of the
 186  * memory controller interleaving feature, where accesses are interleaved
 187  * _BETWEEN_ two seperate memory controllers.  This is configured only in
 188  * CS0_CONFIG[INTLV_CTL] of each memory controller.
 189  *
 190  * memory controller documentation | number of chip selects
 191  *                                 | per memory controller supported
 192  * --------------------------------|-----------------------------------------
 193  * cache line interleaving         | 1 (CS0 only)
 194  * page interleaving               | 1 (CS0 only)
 195  * bank interleaving               | 1 (CS0 only)
 196  * superbank interleraving         | depends on bank (chip select)
 197  *                                 |   interleraving [rank interleaving]
 198  *                                 |   mode used on every memory controller
 199  *
 200  * Even further confusing is the existence of the interleaving feature
 201  * _WITHIN_ each memory controller.  The feature is referred to in
 202  * documentation as chip select interleaving or bank interleaving,
 203  * although it is configured in the DDR_SDRAM_CFG field.
 204  *
 205  * Name of field                | documentation name    | this code
 206  * -----------------------------|-----------------------|------------------
 207  * DDR_SDRAM_CFG[BA_INTLV_CTL]  | Bank (chip select)    | rank interleaving
 208  *                              |  interleaving
 209  */
 210
 211 const char *step_string_tbl[] = {
 212         "STEP_GET_SPD",
 213         "STEP_COMPUTE_DIMM_PARMS",
 214         "STEP_COMPUTE_COMMON_PARMS",
 215         "STEP_GATHER_OPTS",
 216         "STEP_ASSIGN_ADDRESSES",
 217         "STEP_COMPUTE_REGS",
 218         "STEP_PROGRAM_REGS",
 219         "STEP_ALL"
 220 };
 221
 222 const char * step_to_string(unsigned int step) {
 223
 224         unsigned int s = __ilog2(step);
 225
 226         if ((1 << s) != step)
 227                 return step_string_tbl[7];
 228
 229         if (s >= ARRAY_SIZE(step_string_tbl)) {
 230                 printf("Error for the step in %s\n", __func__);
 231                 s = 0;
 232         }
 233
 234         return step_string_tbl[s];
 235 }
 236
 237 static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo,
 238                           unsigned int dbw_cap_adj[])
 239 {
 240         unsigned int i, j;
 241         unsigned long long total_mem, current_mem_base, total_ctlr_mem;
 242         unsigned long long rank_density, ctlr_density = 0;
 243         unsigned int first_ctrl = pinfo->first_ctrl;
 244         unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
 245
 246         /*
 247          * If a reduced data width is requested, but the SPD
 248          * specifies a physically wider device, adjust the
 249          * computed dimm capacities accordingly before
 250          * assigning addresses.
 251          */
 252         for (i = first_ctrl; i <= last_ctrl; i++) {
 253                 unsigned int found = 0;
 254
 255                 switch (pinfo->memctl_opts[i].data_bus_width) {
 256                 case 2:
 257                         /* 16-bit */
 258                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 259                                 unsigned int dw;
 260                                 if (!pinfo->dimm_params[i][j].n_ranks)
 261                                         continue;
 262                                 dw = pinfo->dimm_params[i][j].primary_sdram_width;
 263                                 if ((dw == 72 || dw == 64)) {
 264                                         dbw_cap_adj[i] = 2;
 265                                         break;
 266                                 } else if ((dw == 40 || dw == 32)) {
 267                                         dbw_cap_adj[i] = 1;
 268                                         break;
 269                                 }
 270                         }
 271                         break;
 272
 273                 case 1:
 274                         /* 32-bit */
 275                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 276                                 unsigned int dw;
 277                                 dw = pinfo->dimm_params[i][j].data_width;
 278                                 if (pinfo->dimm_params[i][j].n_ranks
 279                                     && (dw == 72 || dw == 64)) {
 280                                         /*
 281                                          * FIXME: can't really do it
 282                                          * like this because this just
 283                                          * further reduces the memory
 284                                          */
 285                                         found = 1;
 286                                         break;
 287                                 }
 288                         }
 289                         if (found) {
 290                                 dbw_cap_adj[i] = 1;
 291                         }
 292                         break;
 293
 294                 case 0:
 295                         /* 64-bit */
 296                         break;
 297
 298                 default:
 299                         printf("unexpected data bus width "
 300                                 "specified controller %u\n", i);
 301                         return 1;
 302                 }
 303                 debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]);
 304         }
 305
 306         current_mem_base = pinfo->mem_base;
 307         total_mem = 0;
 308         if (pinfo->memctl_opts[first_ctrl].memctl_interleaving) {
 309                 rank_density = pinfo->dimm_params[first_ctrl][0].rank_density >>
 310                                         dbw_cap_adj[first_ctrl];
 311                 switch (pinfo->memctl_opts[first_ctrl].ba_intlv_ctl &
 312                                         FSL_DDR_CS0_CS1_CS2_CS3) {
 313                 case FSL_DDR_CS0_CS1_CS2_CS3:
 314                         ctlr_density = 4 * rank_density;
 315                         break;
 316                 case FSL_DDR_CS0_CS1:
 317                 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
 318                         ctlr_density = 2 * rank_density;
 319                         break;
 320                 case FSL_DDR_CS2_CS3:
 321                 default:
 322                         ctlr_density = rank_density;
 323                         break;
 324                 }
 325                 debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
 326                         rank_density, ctlr_density);
 327                 for (i = first_ctrl; i <= last_ctrl; i++) {
 328                         if (pinfo->memctl_opts[i].memctl_interleaving) {
 329                                 switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
 330                                 case FSL_DDR_256B_INTERLEAVING:
 331                                 case FSL_DDR_CACHE_LINE_INTERLEAVING:
 332                                 case FSL_DDR_PAGE_INTERLEAVING:
 333                                 case FSL_DDR_BANK_INTERLEAVING:
 334                                 case FSL_DDR_SUPERBANK_INTERLEAVING:
 335                                         total_ctlr_mem = 2 * ctlr_density;
 336                                         break;
 337                                 case FSL_DDR_3WAY_1KB_INTERLEAVING:
 338                                 case FSL_DDR_3WAY_4KB_INTERLEAVING:
 339                                 case FSL_DDR_3WAY_8KB_INTERLEAVING:
 340                                         total_ctlr_mem = 3 * ctlr_density;
 341                                         break;
 342                                 case FSL_DDR_4WAY_1KB_INTERLEAVING:
 343                                 case FSL_DDR_4WAY_4KB_INTERLEAVING:
 344                                 case FSL_DDR_4WAY_8KB_INTERLEAVING:
 345                                         total_ctlr_mem = 4 * ctlr_density;
 346                                         break;
 347                                 default:
 348                                         panic("Unknown interleaving mode");
 349                                 }
 350                                 pinfo->common_timing_params[i].base_address =
 351                                                         current_mem_base;
 352                                 pinfo->common_timing_params[i].total_mem =
 353                                                         total_ctlr_mem;
 354                                 total_mem = current_mem_base + total_ctlr_mem;
 355                                 debug("ctrl %d base 0x%llx\n", i, current_mem_base);
 356                                 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
 357                         } else {
 358                                 /* when 3rd controller not interleaved */
 359                                 current_mem_base = total_mem;
 360                                 total_ctlr_mem = 0;
 361                                 pinfo->common_timing_params[i].base_address =
 362                                                         current_mem_base;
 363                                 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 364                                         unsigned long long cap =
 365                                                 pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
 366                                         pinfo->dimm_params[i][j].base_address =
 367                                                 current_mem_base;
 368                                         debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
 369                                         current_mem_base += cap;
 370                                         total_ctlr_mem += cap;
 371                                 }
 372                                 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
 373                                 pinfo->common_timing_params[i].total_mem =
 374                                                         total_ctlr_mem;
 375                                 total_mem += total_ctlr_mem;
 376                         }
 377                 }
 378         } else {
 379                 /*
 380                  * Simple linear assignment if memory
 381                  * controllers are not interleaved.
 382                  */
 383                 for (i = first_ctrl; i <= last_ctrl; i++) {
 384                         total_ctlr_mem = 0;
 385                         pinfo->common_timing_params[i].base_address =
 386                                                 current_mem_base;
 387                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 388                                 /* Compute DIMM base addresses. */
 389                                 unsigned long long cap =
 390                                         pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
 391                                 pinfo->dimm_params[i][j].base_address =
 392                                         current_mem_base;
 393                                 debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
 394                                 current_mem_base += cap;
 395                                 total_ctlr_mem += cap;
 396                         }
 397                         debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
 398                         pinfo->common_timing_params[i].total_mem =
 399                                                         total_ctlr_mem;
 400                         total_mem += total_ctlr_mem;
 401                 }
 402         }
 403         debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
 404
 405         return total_mem;
 406 }
 407
 408 /* Use weak function to allow board file to override the address assignment */
 409 __attribute__((weak, alias("__step_assign_addresses")))
 410 unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
 411                           unsigned int dbw_cap_adj[]);
 412
 413 unsigned long long
 414 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 415                                        unsigned int size_only)
 416 {
 417         unsigned int i, j;
 418         unsigned long long total_mem = 0;
 419         int assert_reset = 0;
 420         unsigned int first_ctrl =  pinfo->first_ctrl;
 421         unsigned int last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
 422         __maybe_unused int retval;
 423         __maybe_unused bool goodspd = false;
 424         __maybe_unused int dimm_slots_per_ctrl = pinfo->dimm_slots_per_ctrl;
 425
 426         fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
 427         common_timing_params_t *timing_params = pinfo->common_timing_params;
 428         if (pinfo->board_need_mem_reset)
 429                 assert_reset = pinfo->board_need_mem_reset();
 430
 431         /* data bus width capacity adjust shift amount */
 432         unsigned int dbw_capacity_adjust[CONFIG_SYS_NUM_DDR_CTLRS];
 433
 434         for (i = first_ctrl; i <= last_ctrl; i++)
 435                 dbw_capacity_adjust[i] = 0;
 436
 437         debug("starting at step %u (%s)\n",
 438               start_step, step_to_string(start_step));
 439
 440         switch (start_step) {
 441         case STEP_GET_SPD:
 442 #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
 443                 /* STEP 1:  Gather all DIMM SPD data */
 444                 for (i = first_ctrl; i <= last_ctrl; i++) {
 445                         fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i,
 446                                         dimm_slots_per_ctrl);
 447                 }
 448
 449         case STEP_COMPUTE_DIMM_PARMS:
 450                 /* STEP 2:  Compute DIMM parameters from SPD data */
 451
 452                 for (i = first_ctrl; i <= last_ctrl; i++) {
 453                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 454                                 generic_spd_eeprom_t *spd =
 455                                         &(pinfo->spd_installed_dimms[i][j]);
 456                                 dimm_params_t *pdimm =
 457                                         &(pinfo->dimm_params[i][j]);
 458                                 retval = compute_dimm_parameters(
 459                                                         i, spd, pdimm, j);
 460 #ifdef CONFIG_SYS_DDR_RAW_TIMING
 461                                 if (!j && retval) {
 462                                         printf("SPD error on controller %d! "
 463                                         "Trying fallback to raw timing "
 464                                         "calculation\n", i);
 465                                         retval = fsl_ddr_get_dimm_params(pdimm,
 466                                                                          i, j);
 467                                 }
 468 #else
 469                                 if (retval == 2) {
 470                                         printf("Error: compute_dimm_parameters"
 471                                         " non-zero returned FATAL value "
 472                                         "for memctl=%u dimm=%u\n", i, j);
 473                                         return 0;
 474                                 }
 475 #endif
 476                                 if (retval) {
 477                                         debug("Warning: compute_dimm_parameters"
 478                                         " non-zero return value for memctl=%u "
 479                                         "dimm=%u\n", i, j);
 480                                 } else {
 481                                         goodspd = true;
 482                                 }
 483                         }
 484                 }
 485                 if (!goodspd) {
 486                         /*
 487                          * No valid SPD found
 488                          * Throw an error if this is for main memory, i.e.
 489                          * first_ctrl == 0. Otherwise, siliently return 0
 490                          * as the memory size.
 491                          */
 492                         if (first_ctrl == 0)
 493                                 printf("Error: No valid SPD detected.\n");
 494
 495                         return 0;
 496                 }
 497 #elif defined(CONFIG_SYS_DDR_RAW_TIMING)
 498         case STEP_COMPUTE_DIMM_PARMS:
 499                 for (i = first_ctrl; i <= last_ctrl; i++) {
 500                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 501                                 dimm_params_t *pdimm =
 502                                         &(pinfo->dimm_params[i][j]);
 503                                 fsl_ddr_get_dimm_params(pdimm, i, j);
 504                         }
 505                 }
 506                 debug("Filling dimm parameters from board specific file\n");
 507 #endif
 508         case STEP_COMPUTE_COMMON_PARMS:
 509                 /*
 510                  * STEP 3: Compute a common set of timing parameters
 511                  * suitable for all of the DIMMs on each memory controller
 512                  */
 513                 for (i = first_ctrl; i <= last_ctrl; i++) {
 514                         debug("Computing lowest common DIMM"
 515                                 " parameters for memctl=%u\n", i);
 516                         compute_lowest_common_dimm_parameters
 517                                 (i,
 518                                  pinfo->dimm_params[i],
 519                                  &timing_params[i],
 520                                  CONFIG_DIMM_SLOTS_PER_CTLR);
 521                 }
 522
 523         case STEP_GATHER_OPTS:
 524                 /* STEP 4:  Gather configuration requirements from user */
 525                 for (i = first_ctrl; i <= last_ctrl; i++) {
 526                         debug("Reloading memory controller "
 527                                 "configuration options for memctl=%u\n", i);
 528                         /*
 529                          * This "reloads" the memory controller options
 530                          * to defaults.  If the user "edits" an option,
 531                          * next_step points to the step after this,
 532                          * which is currently STEP_ASSIGN_ADDRESSES.
 533                          */
 534                         populate_memctl_options(
 535                                         &timing_params[i],
 536                                         &pinfo->memctl_opts[i],
 537                                         pinfo->dimm_params[i], i);
 538                         /*
 539                          * For RDIMMs, JEDEC spec requires clocks to be stable
 540                          * before reset signal is deasserted. For the boards
 541                          * using fixed parameters, this function should be
 542                          * be called from board init file.
 543                          */
 544                         if (timing_params[i].all_dimms_registered)
 545                                 assert_reset = 1;
 546                 }
 547                 if (assert_reset && !size_only) {
 548                         if (pinfo->board_mem_reset) {
 549                                 debug("Asserting mem reset\n");
 550                                 pinfo->board_mem_reset();
 551                         } else {
 552                                 debug("Asserting mem reset missing\n");
 553                         }
 554                 }
 555
 556         case STEP_ASSIGN_ADDRESSES:
 557                 /* STEP 5:  Assign addresses to chip selects */
 558                 check_interleaving_options(pinfo);
 559                 total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust);
 560                 debug("Total mem %llu assigned\n", total_mem);
 561
 562         case STEP_COMPUTE_REGS:
 563                 /* STEP 6:  compute controller register values */
 564                 debug("FSL Memory ctrl register computation\n");
 565                 for (i = first_ctrl; i <= last_ctrl; i++) {
 566                         if (timing_params[i].ndimms_present == 0) {
 567                                 memset(&ddr_reg[i], 0,
 568                                         sizeof(fsl_ddr_cfg_regs_t));
 569                                 continue;
 570                         }
 571
 572                         compute_fsl_memctl_config_regs
 573                                 (i,
 574                                  &pinfo->memctl_opts[i],
 575                                  &ddr_reg[i], &timing_params[i],
 576                                  pinfo->dimm_params[i],
 577                                  dbw_capacity_adjust[i],
 578                                  size_only);
 579                 }
 580
 581         default:
 582                 break;
 583         }
 584
 585         {
 586                 /*
 587                  * Compute the amount of memory available just by
 588                  * looking for the highest valid CSn_BNDS value.
 589                  * This allows us to also experiment with using
 590                  * only CS0 when using dual-rank DIMMs.
 591                  */
 592                 unsigned int max_end = 0;
 593
 594                 for (i = first_ctrl; i <= last_ctrl; i++) {
 595                         for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) {
 596                                 fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
 597                                 if (reg->cs[j].config & 0x80000000) {
 598                                         unsigned int end;
 599                                         /*
 600                                          * 0xfffffff is a special value we put
 601                                          * for unused bnds
 602                                          */
 603                                         if (reg->cs[j].bnds == 0xffffffff)
 604                                                 continue;
 605                                         end = reg->cs[j].bnds & 0xffff;
 606                                         if (end > max_end) {
 607                                                 max_end = end;
 608                                         }
 609                                 }
 610                         }
 611                 }
 612
 613                 total_mem = 1 + (((unsigned long long)max_end << 24ULL) |
 614                             0xFFFFFFULL) - pinfo->mem_base;
 615         }
 616
 617         return total_mem;
 618 }
 619
 620 phys_size_t __fsl_ddr_sdram(fsl_ddr_info_t *pinfo)
 621 {
 622         unsigned int i, first_ctrl, last_ctrl;
 623 #ifdef CONFIG_PPC
 624         unsigned int law_memctl = LAW_TRGT_IF_DDR_1;
 625 #endif
 626         unsigned long long total_memory;
 627         int deassert_reset = 0;
 628
 629         first_ctrl = pinfo->first_ctrl;
 630         last_ctrl = first_ctrl + pinfo->num_ctrls - 1;
 631
 632         /* Compute it once normally. */
 633 #ifdef CONFIG_FSL_DDR_INTERACTIVE
 634         if (tstc() && (getc() == 'd')) {        /* we got a key press of 'd' */
 635                 total_memory = fsl_ddr_interactive(pinfo, 0);
 636         } else if (fsl_ddr_interactive_env_var_exists()) {
 637                 total_memory = fsl_ddr_interactive(pinfo, 1);
 638         } else
 639 #endif
 640                 total_memory = fsl_ddr_compute(pinfo, STEP_GET_SPD, 0);
 641
 642         /* setup 3-way interleaving before enabling DDRC */
 643         switch (pinfo->memctl_opts[first_ctrl].memctl_interleaving_mode) {
 644         case FSL_DDR_3WAY_1KB_INTERLEAVING:
 645         case FSL_DDR_3WAY_4KB_INTERLEAVING:
 646         case FSL_DDR_3WAY_8KB_INTERLEAVING:
 647                 fsl_ddr_set_intl3r(
 648                         pinfo->memctl_opts[first_ctrl].
 649                         memctl_interleaving_mode);
 650                 break;
 651         default:
 652                 break;
 653         }
 654
 655         /*
 656          * Program configuration registers.
 657          * JEDEC specs requires clocks to be stable before deasserting reset
 658          * for RDIMMs. Clocks start after chip select is enabled and clock
 659          * control register is set. During step 1, all controllers have their
 660          * registers set but not enabled. Step 2 proceeds after deasserting
 661          * reset through board FPGA or GPIO.
 662          * For non-registered DIMMs, initialization can go through but it is
 663          * also OK to follow the same flow.
 664          */
 665         if (pinfo->board_need_mem_reset)
 666                 deassert_reset = pinfo->board_need_mem_reset();
 667         for (i = first_ctrl; i <= last_ctrl; i++) {
 668                 if (pinfo->common_timing_params[i].all_dimms_registered)
 669                         deassert_reset = 1;
 670         }
 671         for (i = first_ctrl; i <= last_ctrl; i++) {
 672                 debug("Programming controller %u\n", i);
 673                 if (pinfo->common_timing_params[i].ndimms_present == 0) {
 674                         debug("No dimms present on controller %u; "
 675                                         "skipping programming\n", i);
 676                         continue;
 677                 }
 678                 /*
 679                  * The following call with step = 1 returns before enabling
 680                  * the controller. It has to finish with step = 2 later.
 681                  */
 682                 fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]), i,
 683                                         deassert_reset ? 1 : 0);
 684         }
 685         if (deassert_reset) {
 686                 /* Use board FPGA or GPIO to deassert reset signal */
 687                 if (pinfo->board_mem_de_reset) {
 688                         debug("Deasserting mem reset\n");
 689                         pinfo->board_mem_de_reset();
 690                 } else {
 691                         debug("Deasserting mem reset missing\n");
 692                 }
 693                 for (i = first_ctrl; i <= last_ctrl; i++) {
 694                         /* Call with step = 2 to continue initialization */
 695                         fsl_ddr_set_memctl_regs(&(pinfo->fsl_ddr_config_reg[i]),
 696                                                 i, 2);
 697                 }
 698         }
 699
 700 #ifdef CONFIG_FSL_DDR_SYNC_REFRESH
 701         fsl_ddr_sync_memctl_refresh(first_ctrl, last_ctrl);
 702 #endif
 703
 704 #ifdef CONFIG_PPC
 705         /* program LAWs */
 706         for (i = first_ctrl; i <= last_ctrl; i++) {
 707                 if (pinfo->memctl_opts[i].memctl_interleaving) {
 708                         switch (pinfo->memctl_opts[i].
 709                                 memctl_interleaving_mode) {
 710                         case FSL_DDR_CACHE_LINE_INTERLEAVING:
 711                         case FSL_DDR_PAGE_INTERLEAVING:
 712                         case FSL_DDR_BANK_INTERLEAVING:
 713                         case FSL_DDR_SUPERBANK_INTERLEAVING:
 714                                 if (i % 2)
 715                                         break;
 716                                 if (i == 0) {
 717                                         law_memctl = LAW_TRGT_IF_DDR_INTRLV;
 718                                         fsl_ddr_set_lawbar(
 719                                                 &pinfo->common_timing_params[i],
 720                                                 law_memctl, i);
 721                                 }
 722 #if CONFIG_SYS_NUM_DDR_CTLRS > 3
 723                                 else if (i == 2) {
 724                                         law_memctl = LAW_TRGT_IF_DDR_INTLV_34;
 725                                         fsl_ddr_set_lawbar(
 726                                                 &pinfo->common_timing_params[i],
 727                                                 law_memctl, i);
 728                                 }
 729 #endif
 730                                 break;
 731                         case FSL_DDR_3WAY_1KB_INTERLEAVING:
 732                         case FSL_DDR_3WAY_4KB_INTERLEAVING:
 733                         case FSL_DDR_3WAY_8KB_INTERLEAVING:
 734                                 law_memctl = LAW_TRGT_IF_DDR_INTLV_123;
 735                                 if (i == 0) {
 736                                         fsl_ddr_set_lawbar(
 737                                                 &pinfo->common_timing_params[i],
 738                                                 law_memctl, i);
 739                                 }
 740                                 break;
 741                         case FSL_DDR_4WAY_1KB_INTERLEAVING:
 742                         case FSL_DDR_4WAY_4KB_INTERLEAVING:
 743                         case FSL_DDR_4WAY_8KB_INTERLEAVING:
 744                                 law_memctl = LAW_TRGT_IF_DDR_INTLV_1234;
 745                                 if (i == 0)
 746                                         fsl_ddr_set_lawbar(
 747                                                 &pinfo->common_timing_params[i],
 748                                                 law_memctl, i);
 749                                 /* place holder for future 4-way interleaving */
 750                                 break;
 751                         default:
 752                                 break;
 753                         }
 754                 } else {
 755                         switch (i) {
 756                         case 0:
 757                                 law_memctl = LAW_TRGT_IF_DDR_1;
 758                                 break;
 759                         case 1:
 760                                 law_memctl = LAW_TRGT_IF_DDR_2;
 761                                 break;
 762                         case 2:
 763                                 law_memctl = LAW_TRGT_IF_DDR_3;
 764                                 break;
 765                         case 3:
 766                                 law_memctl = LAW_TRGT_IF_DDR_4;
 767                                 break;
 768                         default:
 769                                 break;
 770                         }
 771                         fsl_ddr_set_lawbar(&pinfo->common_timing_params[i],
 772                                            law_memctl, i);
 773                 }
 774         }
 775 #endif
 776
 777         debug("total_memory by %s = %llu\n", __func__, total_memory);
 778
 779 #if !defined(CONFIG_PHYS_64BIT)
 780         /* Check for 4G or more.  Bad. */
 781         if ((first_ctrl == 0) && (total_memory >= (1ull << 32))) {
 782                 puts("Detected ");
 783                 print_size(total_memory, " of memory\n");
 784                 printf("       This U-Boot only supports < 4G of DDR\n");
 785                 printf("       You could rebuild it with CONFIG_PHYS_64BIT\n");
 786                 printf("       "); /* re-align to match init_dram print */
 787                 total_memory = CONFIG_MAX_MEM_MAPPED;
 788         }
 789 #endif
 790
 791         return total_memory;
 792 }
 793
 794 /*
 795  * fsl_ddr_sdram(void) -- this is the main function to be
 796  * called by dram_init() in the board file.
 797  *
 798  * It returns amount of memory configured in bytes.
 799  */
 800 phys_size_t fsl_ddr_sdram(void)
 801 {
 802         fsl_ddr_info_t info;
 803
 804         /* Reset info structure. */
 805         memset(&info, 0, sizeof(fsl_ddr_info_t));
 806         info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
 807         info.first_ctrl = 0;
 808         info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS;
 809         info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR;
 810         info.board_need_mem_reset = board_need_mem_reset;
 811         info.board_mem_reset = board_assert_mem_reset;
 812         info.board_mem_de_reset = board_deassert_mem_reset;
 813         remove_unused_controllers(&info);
 814
 815         return __fsl_ddr_sdram(&info);
 816 }
 817
 818 #ifdef CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
 819 phys_size_t fsl_other_ddr_sdram(unsigned long long base,
 820                                 unsigned int first_ctrl,
 821                                 unsigned int num_ctrls,
 822                                 unsigned int dimm_slots_per_ctrl,
 823                                 int (*board_need_reset)(void),
 824                                 void (*board_reset)(void),
 825                                 void (*board_de_reset)(void))
 826 {
 827         fsl_ddr_info_t info;
 828
 829         /* Reset info structure. */
 830         memset(&info, 0, sizeof(fsl_ddr_info_t));
 831         info.mem_base = base;
 832         info.first_ctrl = first_ctrl;
 833         info.num_ctrls = num_ctrls;
 834         info.dimm_slots_per_ctrl = dimm_slots_per_ctrl;
 835         info.board_need_mem_reset = board_need_reset;
 836         info.board_mem_reset = board_reset;
 837         info.board_mem_de_reset = board_de_reset;
 838
 839         return __fsl_ddr_sdram(&info);
 840 }
 841 #endif
 842
 843 /*
 844  * fsl_ddr_sdram_size(first_ctrl, last_intlv) - This function only returns the
 845  * size of the total memory without setting ddr control registers.
 846  */
 847 phys_size_t
 848 fsl_ddr_sdram_size(void)
 849 {
 850         fsl_ddr_info_t  info;
 851         unsigned long long total_memory = 0;
 852
 853         memset(&info, 0 , sizeof(fsl_ddr_info_t));
 854         info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY;
 855         info.first_ctrl = 0;
 856         info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS;
 857         info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR;
 858         info.board_need_mem_reset = NULL;
 859         remove_unused_controllers(&info);
 860
 861         /* Compute it once normally. */
 862         total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1);
 863
 864         return total_memory;
 865 }