2 * Copyright (C) Marvell International Ltd. and its affiliates
4 * SPDX-License-Identifier: GPL-2.0
11 #include <asm/arch/cpu.h>
12 #include <asm/arch/soc.h>
14 #include "ddr3_init.h"
16 #define A38X_NUMBER_OF_INTERFACES 5
18 #define SAR_DEV_ID_OFFS 27
19 #define SAR_DEV_ID_MASK 0x7
21 /* Termal Sensor Registers */
22 #define TSEN_STATE_REG 0xe4070
23 #define TSEN_STATE_OFFSET 31
24 #define TSEN_STATE_MASK (0x1 << TSEN_STATE_OFFSET)
25 #define TSEN_CONF_REG 0xe4074
26 #define TSEN_CONF_RST_OFFSET 8
27 #define TSEN_CONF_RST_MASK (0x1 << TSEN_CONF_RST_OFFSET)
28 #define TSEN_STATUS_REG 0xe4078
29 #define TSEN_STATUS_READOUT_VALID_OFFSET 10
30 #define TSEN_STATUS_READOUT_VALID_MASK (0x1 << \
31 TSEN_STATUS_READOUT_VALID_OFFSET)
32 #define TSEN_STATUS_TEMP_OUT_OFFSET 0
33 #define TSEN_STATUS_TEMP_OUT_MASK (0x3ff << TSEN_STATUS_TEMP_OUT_OFFSET)
35 static struct dfx_access interface_map[] = {
51 /* This array hold the board round trip delay (DQ and CK) per <interface,bus> */
52 struct trip_delay_element a38x_board_round_trip_delay_array[] = {
54 /* Interface bus DQS-delay CK-delay */
59 { 4282, 6086 }, /* ECC PUP */
64 { 4282, 6160 }, /* ECC PUP */
67 /* Interface bus DQS-delay CK-delay */
72 { 4282, 6086 }, /* ECC PUP */
77 { 4282, 6160 } /* ECC PUP */
80 #ifdef STATIC_ALGO_SUPPORT
82 static struct trip_delay_element a38x_package_round_trip_delay_array[] = {
83 /* IF BUS DQ_DELAY CK_DELAY */
106 static int a38x_silicon_delay_offset[] = {
116 static u8 a38x_bw_per_freq[DDR_FREQ_LIMIT] = {
117 0x3, /* DDR_FREQ_100 */
118 0x4, /* DDR_FREQ_400 */
119 0x4, /* DDR_FREQ_533 */
120 0x5, /* DDR_FREQ_667 */
121 0x5, /* DDR_FREQ_800 */
122 0x5, /* DDR_FREQ_933 */
123 0x5, /* DDR_FREQ_1066 */
124 0x3, /* DDR_FREQ_311 */
125 0x3, /* DDR_FREQ_333 */
126 0x4, /* DDR_FREQ_467 */
127 0x5, /* DDR_FREQ_850 */
128 0x5, /* DDR_FREQ_600 */
129 0x3, /* DDR_FREQ_300 */
130 0x5, /* DDR_FREQ_900 */
131 0x3, /* DDR_FREQ_360 */
132 0x5 /* DDR_FREQ_1000 */
135 static u8 a38x_rate_per_freq[DDR_FREQ_LIMIT] = {
136 /*TBD*/ 0x1, /* DDR_FREQ_100 */
137 0x2, /* DDR_FREQ_400 */
138 0x2, /* DDR_FREQ_533 */
139 0x2, /* DDR_FREQ_667 */
140 0x2, /* DDR_FREQ_800 */
141 0x3, /* DDR_FREQ_933 */
142 0x3, /* DDR_FREQ_1066 */
143 0x1, /* DDR_FREQ_311 */
144 0x1, /* DDR_FREQ_333 */
145 0x2, /* DDR_FREQ_467 */
146 0x2, /* DDR_FREQ_850 */
147 0x2, /* DDR_FREQ_600 */
148 0x1, /* DDR_FREQ_300 */
149 0x2, /* DDR_FREQ_900 */
150 0x1, /* DDR_FREQ_360 */
151 0x2 /* DDR_FREQ_1000 */
154 static u16 a38x_vco_freq_per_sar[] = {
188 u32 pipe_multicast_mask;
190 u32 dq_bit_map_2_phy_pin[] = {
191 1, 0, 2, 6, 9, 8, 3, 7, /* 0 */
192 8, 9, 1, 7, 2, 6, 3, 0, /* 1 */
193 3, 9, 7, 8, 1, 0, 2, 6, /* 2 */
194 1, 0, 6, 2, 8, 3, 7, 9, /* 3 */
195 0, 1, 2, 9, 7, 8, 3, 6, /* 4 */
198 static int ddr3_tip_a38x_set_divider(u8 dev_num, u32 if_id,
199 enum hws_ddr_freq freq);
202 * Read temperature TJ value
204 u32 ddr3_ctrl_get_junc_temp(u8 dev_num)
208 /* Initiates TSEN hardware reset once */
209 if ((reg_read(TSEN_CONF_REG) & TSEN_CONF_RST_MASK) == 0)
210 reg_bit_set(TSEN_CONF_REG, TSEN_CONF_RST_MASK);
213 /* Check if the readout field is valid */
214 if ((reg_read(TSEN_STATUS_REG) & TSEN_STATUS_READOUT_VALID_MASK) == 0) {
215 printf("%s: TSEN not ready\n", __func__);
219 reg = reg_read(TSEN_STATUS_REG);
220 reg = (reg & TSEN_STATUS_TEMP_OUT_MASK) >> TSEN_STATUS_TEMP_OUT_OFFSET;
222 return ((((10000 * reg) / 21445) * 1000) - 272674) / 1000;
226 * Name: ddr3_tip_a38x_get_freq_config.
230 * Returns: MV_OK if success, other error code if fail.
232 int ddr3_tip_a38x_get_freq_config(u8 dev_num, enum hws_ddr_freq freq,
233 struct hws_tip_freq_config_info
236 if (a38x_bw_per_freq[freq] == 0xff)
237 return MV_NOT_SUPPORTED;
239 if (freq_config_info == NULL)
242 freq_config_info->bw_per_freq = a38x_bw_per_freq[freq];
243 freq_config_info->rate_per_freq = a38x_rate_per_freq[freq];
244 freq_config_info->is_supported = 1;
250 * Name: ddr3_tip_a38x_pipe_enable.
254 * Returns: MV_OK if success, other error code if fail.
256 int ddr3_tip_a38x_pipe_enable(u8 dev_num, enum hws_access_type interface_access,
257 u32 if_id, int enable)
259 u32 data_value, pipe_enable_mask = 0;
262 pipe_enable_mask = 0;
264 if (interface_access == ACCESS_TYPE_MULTICAST)
265 pipe_enable_mask = pipe_multicast_mask;
267 pipe_enable_mask = (1 << interface_map[if_id].pipe);
270 CHECK_STATUS(ddr3_tip_reg_read
271 (dev_num, PIPE_ENABLE_ADDR, &data_value, MASK_ALL_BITS));
272 data_value = (data_value & (~0xff)) | pipe_enable_mask;
273 CHECK_STATUS(ddr3_tip_reg_write(dev_num, PIPE_ENABLE_ADDR, data_value));
279 * Name: ddr3_tip_a38x_if_write.
283 * Returns: MV_OK if success, other error code if fail.
285 int ddr3_tip_a38x_if_write(u8 dev_num, enum hws_access_type interface_access,
286 u32 if_id, u32 reg_addr, u32 data_value,
291 if (mask != MASK_ALL_BITS) {
292 CHECK_STATUS(ddr3_tip_a38x_if_read
293 (dev_num, ACCESS_TYPE_UNICAST, if_id, reg_addr,
294 &ui_data_read, MASK_ALL_BITS));
295 data_value = (ui_data_read & (~mask)) | (data_value & mask);
298 reg_write(reg_addr, data_value);
304 * Name: ddr3_tip_a38x_if_read.
308 * Returns: MV_OK if success, other error code if fail.
310 int ddr3_tip_a38x_if_read(u8 dev_num, enum hws_access_type interface_access,
311 u32 if_id, u32 reg_addr, u32 *data, u32 mask)
313 *data = reg_read(reg_addr) & mask;
319 * Name: ddr3_tip_a38x_select_ddr_controller.
320 * Desc: Enable/Disable access to Marvell's server.
321 * Args: dev_num - device number
322 * enable - whether to enable or disable the server
324 * Returns: MV_OK if success, other error code if fail.
326 int ddr3_tip_a38x_select_ddr_controller(u8 dev_num, int enable)
330 reg = reg_read(CS_ENABLE_REG);
337 reg_write(CS_ENABLE_REG, reg);
343 * Name: ddr3_tip_init_a38x_silicon.
344 * Desc: init Training SW DB.
347 * Returns: MV_OK if success, other error code if fail.
349 static int ddr3_tip_init_a38x_silicon(u32 dev_num, u32 board_id)
351 struct hws_tip_config_func_db config_func;
352 enum hws_ddr_freq ddr_freq;
354 struct hws_topology_map *tm = ddr3_get_topology_map();
356 /* new read leveling version */
357 config_func.tip_dunit_read_func = ddr3_tip_a38x_if_read;
358 config_func.tip_dunit_write_func = ddr3_tip_a38x_if_write;
359 config_func.tip_dunit_mux_select_func =
360 ddr3_tip_a38x_select_ddr_controller;
361 config_func.tip_get_freq_config_info_func =
362 ddr3_tip_a38x_get_freq_config;
363 config_func.tip_set_freq_divider_func = ddr3_tip_a38x_set_divider;
364 config_func.tip_get_device_info_func = ddr3_tip_a38x_get_device_info;
365 config_func.tip_get_temperature = ddr3_ctrl_get_junc_temp;
367 ddr3_tip_init_config_func(dev_num, &config_func);
369 ddr3_tip_register_dq_table(dev_num, dq_bit_map_2_phy_pin);
371 #ifdef STATIC_ALGO_SUPPORT
373 struct hws_tip_static_config_info static_config;
375 board_id * A38X_NUMBER_OF_INTERFACES *
376 tm->num_of_bus_per_interface;
378 static_config.silicon_delay =
379 a38x_silicon_delay_offset[board_id];
380 static_config.package_trace_arr =
381 a38x_package_round_trip_delay_array;
382 static_config.board_trace_arr =
383 &a38x_board_round_trip_delay_array[board_offset];
384 ddr3_tip_init_static_config_db(dev_num, &static_config);
387 status = ddr3_tip_a38x_get_init_freq(dev_num, &ddr_freq);
388 if (MV_OK != status) {
389 DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR,
390 ("DDR3 silicon get target frequency - FAILED 0x%x\n",
396 mask_tune_func = (SET_LOW_FREQ_MASK_BIT |
397 LOAD_PATTERN_MASK_BIT |
398 SET_MEDIUM_FREQ_MASK_BIT | WRITE_LEVELING_MASK_BIT |
399 /* LOAD_PATTERN_2_MASK_BIT | */
400 WRITE_LEVELING_SUPP_MASK_BIT |
401 READ_LEVELING_MASK_BIT |
404 SET_TARGET_FREQ_MASK_BIT |
405 WRITE_LEVELING_TF_MASK_BIT |
406 WRITE_LEVELING_SUPP_TF_MASK_BIT |
407 READ_LEVELING_TF_MASK_BIT |
408 CENTRALIZATION_RX_MASK_BIT |
409 CENTRALIZATION_TX_MASK_BIT);
412 if ((ddr_freq == DDR_FREQ_333) || (ddr_freq == DDR_FREQ_400)) {
413 mask_tune_func = (WRITE_LEVELING_MASK_BIT |
414 LOAD_PATTERN_2_MASK_BIT |
415 WRITE_LEVELING_SUPP_MASK_BIT |
416 READ_LEVELING_MASK_BIT |
419 CENTRALIZATION_RX_MASK_BIT |
420 CENTRALIZATION_TX_MASK_BIT);
421 rl_mid_freq_wa = 0; /* WA not needed if 333/400 is TF */
424 /* Supplementary not supported for ECC modes */
425 if (1 == ddr3_if_ecc_enabled()) {
426 mask_tune_func &= ~WRITE_LEVELING_SUPP_TF_MASK_BIT;
427 mask_tune_func &= ~WRITE_LEVELING_SUPP_MASK_BIT;
428 mask_tune_func &= ~PBS_TX_MASK_BIT;
429 mask_tune_func &= ~PBS_RX_MASK_BIT;
434 if (ck_delay_16 == -1)
439 calibration_update_control = 1;
441 init_freq = tm->interface_params[first_active_if].memory_freq;
443 ddr3_tip_a38x_get_medium_freq(dev_num, &medium_freq);
448 int ddr3_a38x_update_topology_map(u32 dev_num, struct hws_topology_map *tm)
451 enum hws_ddr_freq freq;
453 ddr3_tip_a38x_get_init_freq(dev_num, &freq);
454 tm->interface_params[if_id].memory_freq = freq;
457 * re-calc topology parameters according to topology updates
460 CHECK_STATUS(hws_ddr3_tip_load_topology_map(dev_num, tm));
465 int ddr3_tip_init_a38x(u32 dev_num, u32 board_id)
467 struct hws_topology_map *tm = ddr3_get_topology_map();
472 ddr3_a38x_update_topology_map(dev_num, tm);
473 ddr3_tip_init_a38x_silicon(dev_num, board_id);
478 int ddr3_tip_a38x_get_init_freq(int dev_num, enum hws_ddr_freq *freq)
482 /* Read sample at reset setting */
483 reg = (reg_read(REG_DEVICE_SAR1_ADDR) >>
484 RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET) &
485 RST2_CPU_DDR_CLOCK_SELECT_IN_MASK;
489 *freq = DDR_FREQ_333;
493 *freq = DDR_FREQ_400;
497 *freq = DDR_FREQ_533;
500 *freq = DDR_FREQ_600;
505 *freq = DDR_FREQ_667;
510 *freq = DDR_FREQ_800;
513 *freq = DDR_FREQ_933;
516 *freq = DDR_FREQ_900;
519 *freq = DDR_FREQ_900;
523 return MV_NOT_SUPPORTED;
529 int ddr3_tip_a38x_get_medium_freq(int dev_num, enum hws_ddr_freq *freq)
533 /* Read sample at reset setting */
534 reg = (reg_read(REG_DEVICE_SAR1_ADDR) >>
535 RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET) &
536 RST2_CPU_DDR_CLOCK_SELECT_IN_MASK;
540 /* Medium is same as TF to run PBS in this freq */
541 *freq = DDR_FREQ_333;
545 /* Medium is same as TF to run PBS in this freq */
546 *freq = DDR_FREQ_400;
550 *freq = DDR_FREQ_533;
555 *freq = DDR_FREQ_333;
560 *freq = DDR_FREQ_400;
563 *freq = DDR_FREQ_300;
566 *freq = DDR_FREQ_360;
569 *freq = DDR_FREQ_400;
573 return MV_NOT_SUPPORTED;
579 u32 ddr3_tip_get_init_freq(void)
581 enum hws_ddr_freq freq;
583 ddr3_tip_a38x_get_init_freq(0, &freq);
588 static int ddr3_tip_a38x_set_divider(u8 dev_num, u32 if_id,
589 enum hws_ddr_freq frequency)
595 DEBUG_TRAINING_ACCESS(DEBUG_LEVEL_ERROR,
596 ("A38x does not support interface 0x%x\n",
601 /* get VCO freq index */
602 sar_val = (reg_read(REG_DEVICE_SAR1_ADDR) >>
603 RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET) &
604 RST2_CPU_DDR_CLOCK_SELECT_IN_MASK;
605 divider = a38x_vco_freq_per_sar[sar_val] / freq_val[frequency];
608 CHECK_STATUS(ddr3_tip_a38x_if_write
609 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x20220, 0x0,
611 CHECK_STATUS(ddr3_tip_a38x_if_write
612 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe42f4, 0x0,
615 /* cpupll_clkdiv_reset_mask */
616 CHECK_STATUS(ddr3_tip_a38x_if_write
617 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4264, 0x1f,
620 /* cpupll_clkdiv_reload_smooth */
621 CHECK_STATUS(ddr3_tip_a38x_if_write
622 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4260,
623 (0x2 << 8), (0xff << 8)));
625 /* cpupll_clkdiv_relax_en */
626 CHECK_STATUS(ddr3_tip_a38x_if_write
627 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4260,
628 (0x2 << 24), (0xff << 24)));
630 /* write the divider */
631 CHECK_STATUS(ddr3_tip_a38x_if_write
632 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4268,
633 (divider << 8), (0x3f << 8)));
635 /* set cpupll_clkdiv_reload_ratio */
636 CHECK_STATUS(ddr3_tip_a38x_if_write
637 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4264,
638 (1 << 8), (1 << 8)));
640 /* undet cpupll_clkdiv_reload_ratio */
641 CHECK_STATUS(ddr3_tip_a38x_if_write
642 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4264, 0,
645 /* clear cpupll_clkdiv_reload_force */
646 CHECK_STATUS(ddr3_tip_a38x_if_write
647 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4260, 0,
650 /* clear cpupll_clkdiv_relax_en */
651 CHECK_STATUS(ddr3_tip_a38x_if_write
652 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4260, 0,
655 /* clear cpupll_clkdiv_reset_mask */
656 CHECK_STATUS(ddr3_tip_a38x_if_write
657 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0xe4264, 0,
660 /* Dunit training clock + 1:1 mode */
661 if ((frequency == DDR_FREQ_LOW_FREQ) || (freq_val[frequency] <= 400)) {
662 CHECK_STATUS(ddr3_tip_a38x_if_write
663 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x18488,
664 (1 << 16), (1 << 16)));
665 CHECK_STATUS(ddr3_tip_a38x_if_write
666 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x1524,
667 (0 << 15), (1 << 15)));
669 CHECK_STATUS(ddr3_tip_a38x_if_write
670 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x18488,
672 CHECK_STATUS(ddr3_tip_a38x_if_write
673 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x1524,
674 (1 << 15), (1 << 15)));
681 * external read from memory
683 int ddr3_tip_ext_read(u32 dev_num, u32 if_id, u32 reg_addr,
684 u32 num_of_bursts, u32 *data)
688 for (burst_num = 0; burst_num < num_of_bursts * 8; burst_num++)
689 data[burst_num] = readl(reg_addr + 4 * burst_num);
695 * external write to memory
697 int ddr3_tip_ext_write(u32 dev_num, u32 if_id, u32 reg_addr,
698 u32 num_of_bursts, u32 *data) {
701 for (burst_num = 0; burst_num < num_of_bursts * 8; burst_num++)
702 writel(data[burst_num], reg_addr + 4 * burst_num);
707 int ddr3_silicon_pre_init(void)
711 result = ddr3_silicon_init();
716 int ddr3_post_run_alg(void)
721 int ddr3_silicon_post_init(void)
723 struct hws_topology_map *tm = ddr3_get_topology_map();
725 /* Set half bus width */
726 if (DDR3_IS_16BIT_DRAM_MODE(tm->bus_act_mask)) {
727 CHECK_STATUS(ddr3_tip_if_write
728 (0, ACCESS_TYPE_UNICAST, PARAM_NOT_CARE,
729 REG_SDRAM_CONFIG_ADDR, 0x0, 0x8000));
735 int ddr3_tip_a38x_get_device_info(u8 dev_num, struct ddr3_device_info *info_ptr)
737 info_ptr->device_id = 0x6800;
738 info_ptr->ck_delay = ck_delay;