2 * Copyright (C) Marvell International Ltd. and its affiliates
4 * SPDX-License-Identifier: GPL-2.0
10 #define MAX_INTERFACE_NUM 1
13 #include "ddr3_hws_hw_training_def.h"
15 /* Allow topolgy update from board TWSI device*/
16 #if !defined(CONFIG_CUSTOMER_BOARD_SUPPORT)
17 #define MV_DDR_TOPOLOGY_UPDATE_FROM_TWSI
22 /* right now, we're not supporting this in mainline */
23 #undef SUPPORT_STATIC_DUNIT_CONFIG
25 /* Controler bus divider 1 for 32 bit, 2 for 64 bit */
26 #define DDR_CONTROLLER_BUS_WIDTH_MULTIPLIER 1
28 /* Tune internal training params values */
29 #define TUNE_TRAINING_PARAMS_CK_DELAY 160
30 #define TUNE_TRAINING_PARAMS_CK_DELAY_16 160
31 #define TUNE_TRAINING_PARAMS_PFINGER 41
32 #define TUNE_TRAINING_PARAMS_NFINGER 43
33 #define TUNE_TRAINING_PARAMS_PHYREG3VAL 0xa
35 #define MARVELL_BOARD MARVELL_BOARD_ID_BASE
38 #define REG_DEVICE_SAR1_ADDR 0xe4204
39 #define RST2_CPU_DDR_CLOCK_SELECT_IN_OFFSET 17
40 #define RST2_CPU_DDR_CLOCK_SELECT_IN_MASK 0x1f
43 #define REG_XBAR_WIN_5_CTRL_ADDR 0x20050
44 #define REG_XBAR_WIN_5_BASE_ADDR 0x20054
47 #define REG_XBAR_WIN_4_CTRL_ADDR 0x20040
48 #define REG_XBAR_WIN_4_BASE_ADDR 0x20044
49 #define REG_XBAR_WIN_4_REMAP_ADDR 0x20048
50 #define REG_XBAR_WIN_7_REMAP_ADDR 0x20078
51 #define REG_XBAR_WIN_16_CTRL_ADDR 0x200d0
52 #define REG_XBAR_WIN_16_BASE_ADDR 0x200d4
53 #define REG_XBAR_WIN_16_REMAP_ADDR 0x200dc
54 #define REG_XBAR_WIN_19_CTRL_ADDR 0x200e8
56 #define REG_FASTPATH_WIN_BASE_ADDR(win) (0x20180 + (0x8 * win))
57 #define REG_FASTPATH_WIN_CTRL_ADDR(win) (0x20184 + (0x8 * win))
59 /* SatR defined too change topology busWidth and ECC configuration */
60 #define DDR_SATR_CONFIG_MASK_WIDTH 0x8
61 #define DDR_SATR_CONFIG_MASK_ECC 0x10
62 #define DDR_SATR_CONFIG_MASK_ECC_PUP 0x20
64 #define REG_SAMPLE_RESET_HIGH_ADDR 0x18600
66 #define MV_BOARD_REFCLK MV_BOARD_REFCLK_25MHZ
68 /* Matrix enables DRAM modes (bus width/ECC) per boardId */
69 #define TOPOLOGY_UPDATE_32BIT 0
70 #define TOPOLOGY_UPDATE_32BIT_ECC 1
71 #define TOPOLOGY_UPDATE_16BIT 2
72 #define TOPOLOGY_UPDATE_16BIT_ECC 3
73 #define TOPOLOGY_UPDATE_16BIT_ECC_PUP3 4
74 #define TOPOLOGY_UPDATE { \
75 /* 32Bit, 32bit ECC, 16bit, 16bit ECC PUP4, 16bit ECC PUP3 */ \
76 {1, 1, 1, 1, 1}, /* RD_NAS_68XX_ID */ \
77 {1, 1, 1, 1, 1}, /* DB_68XX_ID */ \
78 {1, 0, 1, 0, 1}, /* RD_AP_68XX_ID */ \
79 {1, 0, 1, 0, 1}, /* DB_AP_68XX_ID */ \
80 {1, 0, 1, 0, 1}, /* DB_GP_68XX_ID */ \
81 {0, 0, 1, 1, 0}, /* DB_BP_6821_ID */ \
82 {1, 1, 1, 1, 1} /* DB_AMC_6820_ID */ \
86 CPU_1066MHZ_DDR_400MHZ,
87 CPU_RESERVED_DDR_RESERVED0,
88 CPU_667MHZ_DDR_667MHZ,
89 CPU_800MHZ_DDR_800MHZ,
90 CPU_RESERVED_DDR_RESERVED1,
91 CPU_RESERVED_DDR_RESERVED2,
92 CPU_RESERVED_DDR_RESERVED3,
96 #define ACTIVE_INTERFACE_MASK 0x1
98 #endif /* _DDR3_A38X_H */