2 * Copyright (C) Marvell International Ltd. and its affiliates
4 * SPDX-License-Identifier: GPL-2.0
11 #include <asm/arch/cpu.h>
12 #include <asm/arch/soc.h>
14 #include "ddr3_init.h"
17 u8 debug_pbs = DEBUG_LEVEL_ERROR;
20 * API to change flags outside of the lib
23 /* Debug flags for other Training modules */
24 u8 debug_training_static = DEBUG_LEVEL_ERROR;
25 u8 debug_training = DEBUG_LEVEL_ERROR;
26 u8 debug_leveling = DEBUG_LEVEL_ERROR;
27 u8 debug_centralization = DEBUG_LEVEL_ERROR;
28 u8 debug_training_ip = DEBUG_LEVEL_ERROR;
29 u8 debug_training_bist = DEBUG_LEVEL_ERROR;
30 u8 debug_training_hw_alg = DEBUG_LEVEL_ERROR;
31 u8 debug_training_access = DEBUG_LEVEL_ERROR;
32 u8 debug_training_a38x = DEBUG_LEVEL_ERROR;
34 void ddr3_hws_set_log_level(enum ddr_lib_debug_block block, u8 level)
37 case DEBUG_BLOCK_STATIC:
38 debug_training_static = level;
40 case DEBUG_BLOCK_TRAINING_MAIN:
41 debug_training = level;
43 case DEBUG_BLOCK_LEVELING:
44 debug_leveling = level;
46 case DEBUG_BLOCK_CENTRALIZATION:
47 debug_centralization = level;
53 debug_training_hw_alg = level;
55 case DEBUG_BLOCK_DEVICE:
56 debug_training_a38x = level;
58 case DEBUG_BLOCK_ACCESS:
59 debug_training_access = level;
61 case DEBUG_STAGES_REG_DUMP:
62 if (level == DEBUG_LEVEL_TRACE)
69 debug_training_static = level;
70 debug_training = level;
71 debug_leveling = level;
72 debug_centralization = level;
74 debug_training_hw_alg = level;
75 debug_training_access = level;
76 debug_training_a38x = level;
80 void ddr3_hws_set_log_level(enum ddr_lib_debug_block block, u8 level)
86 struct hws_tip_config_func_db config_func_info[HWS_MAX_DEVICE_NUM];
87 u8 is_default_centralization = 0;
88 u8 is_tune_result = 0;
89 u8 is_validate_window_per_if = 0;
90 u8 is_validate_window_per_pup = 0;
92 u32 is_bist_reset_bit = 1;
93 static struct hws_xsb_info xsb_info[HWS_MAX_DEVICE_NUM];
96 * Dump Dunit & Phy registers
98 int ddr3_tip_reg_dump(u32 dev_num)
100 u32 if_id, reg_addr, data_value, bus_id;
101 u32 read_data[MAX_INTERFACE_NUM];
102 struct hws_topology_map *tm = ddr3_get_topology_map();
104 printf("-- dunit registers --\n");
105 for (reg_addr = 0x1400; reg_addr < 0x19f0; reg_addr += 4) {
106 printf("0x%x ", reg_addr);
107 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
108 VALIDATE_ACTIVE(tm->if_act_mask, if_id);
109 CHECK_STATUS(ddr3_tip_if_read
110 (dev_num, ACCESS_TYPE_UNICAST,
111 if_id, reg_addr, read_data,
113 printf("0x%x ", read_data[if_id]);
118 printf("-- Phy registers --\n");
119 for (reg_addr = 0; reg_addr <= 0xff; reg_addr++) {
120 printf("0x%x ", reg_addr);
121 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
122 VALIDATE_ACTIVE(tm->if_act_mask, if_id);
124 bus_id < tm->num_of_bus_per_interface;
126 VALIDATE_ACTIVE(tm->bus_act_mask, bus_id);
127 CHECK_STATUS(ddr3_tip_bus_read
129 ACCESS_TYPE_UNICAST, bus_id,
130 DDR_PHY_DATA, reg_addr,
132 printf("0x%x ", data_value);
135 bus_id < tm->num_of_bus_per_interface;
137 VALIDATE_ACTIVE(tm->bus_act_mask, bus_id);
138 CHECK_STATUS(ddr3_tip_bus_read
140 ACCESS_TYPE_UNICAST, bus_id,
141 DDR_PHY_CONTROL, reg_addr,
143 printf("0x%x ", data_value);
153 * Register access func registration
155 int ddr3_tip_init_config_func(u32 dev_num,
156 struct hws_tip_config_func_db *config_func)
158 if (config_func == NULL)
161 memcpy(&config_func_info[dev_num], config_func,
162 sizeof(struct hws_tip_config_func_db));
168 * Get training result info pointer
170 enum hws_result *ddr3_tip_get_result_ptr(u32 stage)
172 return training_result[stage];
178 int ddr3_tip_get_device_info(u32 dev_num, struct ddr3_device_info *info_ptr)
180 if (config_func_info[dev_num].tip_get_device_info_func != NULL) {
181 return config_func_info[dev_num].
182 tip_get_device_info_func((u8) dev_num, info_ptr);
188 #ifndef EXCLUDE_SWITCH_DEBUG
190 * Convert freq to character string
192 static char *convert_freq(enum hws_ddr_freq freq)
195 case DDR_FREQ_LOW_FREQ:
196 return "DDR_FREQ_LOW_FREQ";
229 return "DDR_FREQ_360";
232 return "DDR_FREQ_1000";
234 return "Unknown Frequency";
239 * Convert device ID to character string
241 static char *convert_dev_id(u32 dev_id)
254 return "Unknown Device";
259 * Convert device ID to character string
261 static char *convert_mem_size(u32 dev_id)
276 return "wrong mem size";
280 int print_device_info(u8 dev_num)
282 struct ddr3_device_info info_ptr;
283 struct hws_topology_map *tm = ddr3_get_topology_map();
285 CHECK_STATUS(ddr3_tip_get_device_info(dev_num, &info_ptr));
286 printf("=== DDR setup START===\n");
287 printf("\tDevice ID: %s\n", convert_dev_id(info_ptr.device_id));
288 printf("\tDDR3 CK delay: %d\n", info_ptr.ck_delay);
290 printf("=== DDR setup END===\n");
295 void hws_ddr3_tip_sweep_test(int enable)
298 is_validate_window_per_if = 1;
299 is_validate_window_per_pup = 1;
300 debug_training = DEBUG_LEVEL_TRACE;
302 is_validate_window_per_if = 0;
303 is_validate_window_per_pup = 0;
308 char *ddr3_tip_convert_tune_result(enum hws_result tune_result)
310 switch (tune_result) {
316 return "NOT COMPLETED";
325 int ddr3_tip_print_log(u32 dev_num, u32 mem_addr)
328 struct hws_topology_map *tm = ddr3_get_topology_map();
330 #ifndef EXCLUDE_SWITCH_DEBUG
331 if ((is_validate_window_per_if != 0) ||
332 (is_validate_window_per_pup != 0)) {
334 enum hws_ddr_freq freq;
336 freq = tm->interface_params[first_active_if].memory_freq;
338 is_pup_log = (is_validate_window_per_pup != 0) ? 1 : 0;
339 printf("===VALIDATE WINDOW LOG START===\n");
340 printf("DDR Frequency: %s ======\n", convert_freq(freq));
341 /* print sweep windows */
342 ddr3_tip_run_sweep_test(dev_num, sweep_cnt, 1, is_pup_log);
343 ddr3_tip_run_sweep_test(dev_num, sweep_cnt, 0, is_pup_log);
344 ddr3_tip_print_all_pbs_result(dev_num);
345 ddr3_tip_print_wl_supp_result(dev_num);
346 printf("===VALIDATE WINDOW LOG END ===\n");
347 CHECK_STATUS(ddr3_tip_restore_dunit_regs(dev_num));
348 ddr3_tip_reg_dump(dev_num);
352 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
353 VALIDATE_ACTIVE(tm->if_act_mask, if_id);
355 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
356 ("IF %d Status:\n", if_id));
358 if (mask_tune_func & INIT_CONTROLLER_MASK_BIT) {
359 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
360 ("\tInit Controller: %s\n",
361 ddr3_tip_convert_tune_result
362 (training_result[INIT_CONTROLLER]
365 if (mask_tune_func & SET_LOW_FREQ_MASK_BIT) {
366 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
367 ("\tLow freq Config: %s\n",
368 ddr3_tip_convert_tune_result
369 (training_result[SET_LOW_FREQ]
372 if (mask_tune_func & LOAD_PATTERN_MASK_BIT) {
373 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
374 ("\tLoad Pattern: %s\n",
375 ddr3_tip_convert_tune_result
376 (training_result[LOAD_PATTERN]
379 if (mask_tune_func & SET_MEDIUM_FREQ_MASK_BIT) {
380 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
381 ("\tMedium freq Config: %s\n",
382 ddr3_tip_convert_tune_result
383 (training_result[SET_MEDIUM_FREQ]
386 if (mask_tune_func & WRITE_LEVELING_MASK_BIT) {
387 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
389 ddr3_tip_convert_tune_result
390 (training_result[WRITE_LEVELING]
393 if (mask_tune_func & LOAD_PATTERN_2_MASK_BIT) {
394 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
395 ("\tLoad Pattern: %s\n",
396 ddr3_tip_convert_tune_result
397 (training_result[LOAD_PATTERN_2]
400 if (mask_tune_func & READ_LEVELING_MASK_BIT) {
401 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
403 ddr3_tip_convert_tune_result
404 (training_result[READ_LEVELING]
407 if (mask_tune_func & WRITE_LEVELING_SUPP_MASK_BIT) {
408 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
410 ddr3_tip_convert_tune_result
411 (training_result[WRITE_LEVELING_SUPP]
414 if (mask_tune_func & PBS_RX_MASK_BIT) {
415 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
417 ddr3_tip_convert_tune_result
418 (training_result[PBS_RX]
421 if (mask_tune_func & PBS_TX_MASK_BIT) {
422 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
424 ddr3_tip_convert_tune_result
425 (training_result[PBS_TX]
428 if (mask_tune_func & SET_TARGET_FREQ_MASK_BIT) {
429 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
430 ("\tTarget freq Config: %s\n",
431 ddr3_tip_convert_tune_result
432 (training_result[SET_TARGET_FREQ]
435 if (mask_tune_func & WRITE_LEVELING_TF_MASK_BIT) {
436 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
438 ddr3_tip_convert_tune_result
439 (training_result[WRITE_LEVELING_TF]
442 if (mask_tune_func & READ_LEVELING_TF_MASK_BIT) {
443 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
445 ddr3_tip_convert_tune_result
446 (training_result[READ_LEVELING_TF]
449 if (mask_tune_func & WRITE_LEVELING_SUPP_TF_MASK_BIT) {
450 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
451 ("\tWL TF Supp: %s\n",
452 ddr3_tip_convert_tune_result
454 [WRITE_LEVELING_SUPP_TF]
457 if (mask_tune_func & CENTRALIZATION_RX_MASK_BIT) {
458 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
460 ddr3_tip_convert_tune_result
461 (training_result[CENTRALIZATION_RX]
464 if (mask_tune_func & VREF_CALIBRATION_MASK_BIT) {
465 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
466 ("\tVREF_CALIBRATION: %s\n",
467 ddr3_tip_convert_tune_result
468 (training_result[VREF_CALIBRATION]
471 if (mask_tune_func & CENTRALIZATION_TX_MASK_BIT) {
472 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
474 ddr3_tip_convert_tune_result
475 (training_result[CENTRALIZATION_TX]
484 * Print stability log info
486 int ddr3_tip_print_stability_log(u32 dev_num)
488 u8 if_id = 0, csindex = 0, bus_id = 0, idx = 0;
490 u32 read_data[MAX_INTERFACE_NUM];
491 u32 max_cs = hws_ddr3_tip_max_cs_get();
492 struct hws_topology_map *tm = ddr3_get_topology_map();
495 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
496 VALIDATE_ACTIVE(tm->if_act_mask, if_id);
497 printf("Title: I/F# , Tj, Calibration_n0, Calibration_p0, Calibration_n1, Calibration_p1, Calibration_n2, Calibration_p2,");
498 for (csindex = 0; csindex < max_cs; csindex++) {
499 printf("CS%d , ", csindex);
501 VALIDATE_ACTIVE(tm->bus_act_mask, bus_id);
502 printf("VWTx, VWRx, WL_tot, WL_ADLL, WL_PH, RL_Tot, RL_ADLL, RL_PH, RL_Smp, Cen_tx, Cen_rx, Vref, DQVref,");
504 for (idx = 0; idx < 11; idx++)
505 printf("PBSTx-Pad%d,", idx);
507 for (idx = 0; idx < 11; idx++)
508 printf("PBSRx-Pad%d,", idx);
514 for (if_id = 0; if_id < MAX_INTERFACE_NUM; if_id++) {
515 VALIDATE_ACTIVE(tm->if_act_mask, if_id);
517 printf("Data: %d,%d,", if_id,
518 (config_func_info[dev_num].tip_get_temperature != NULL)
519 ? (config_func_info[dev_num].
520 tip_get_temperature(dev_num)) : (0));
522 CHECK_STATUS(ddr3_tip_if_read
523 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x14c8,
524 read_data, MASK_ALL_BITS));
525 printf("%d,%d,", ((read_data[if_id] & 0x3f0) >> 4),
526 ((read_data[if_id] & 0xfc00) >> 10));
527 CHECK_STATUS(ddr3_tip_if_read
528 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x17c8,
529 read_data, MASK_ALL_BITS));
530 printf("%d,%d,", ((read_data[if_id] & 0x3f0) >> 4),
531 ((read_data[if_id] & 0xfc00) >> 10));
532 CHECK_STATUS(ddr3_tip_if_read
533 (dev_num, ACCESS_TYPE_UNICAST, if_id, 0x1dc8,
534 read_data, MASK_ALL_BITS));
535 printf("%d,%d,", ((read_data[if_id] & 0x3f0000) >> 16),
536 ((read_data[if_id] & 0xfc00000) >> 22));
538 for (csindex = 0; csindex < max_cs; csindex++) {
539 printf("CS%d , ", csindex);
540 for (bus_id = 0; bus_id < MAX_BUS_NUM; bus_id++) {
542 VALIDATE_ACTIVE(tm->bus_act_mask, bus_id);
543 ddr3_tip_bus_read(dev_num, if_id,
545 bus_id, DDR_PHY_DATA,
546 RESULT_DB_PHY_REG_ADDR +
548 printf("%d,%d,", (reg_data & 0x1f),
549 ((reg_data & 0x3e0) >> 5));
551 ddr3_tip_bus_read(dev_num, if_id,
553 bus_id, DDR_PHY_DATA,
555 csindex * 4, ®_data);
558 ((reg_data & 0x1c0) >> 6) * 32,
560 (reg_data & 0x1c0) >> 6);
562 CHECK_STATUS(ddr3_tip_if_read
563 (dev_num, ACCESS_TYPE_UNICAST,
565 READ_DATA_SAMPLE_DELAY,
566 read_data, MASK_ALL_BITS));
569 (0xf << (4 * csindex))) >>
571 ddr3_tip_bus_read(dev_num, if_id,
572 ACCESS_TYPE_UNICAST, bus_id,
574 RL_PHY_REG + csindex * 4,
576 printf("%d,%d,%d,%d,",
578 ((reg_data & 0x1c0) >> 6) * 32 +
579 read_data[if_id] * 64,
581 ((reg_data & 0x1c0) >> 6),
584 ddr3_tip_bus_read(dev_num, if_id,
585 ACCESS_TYPE_UNICAST, bus_id,
587 WRITE_CENTRALIZATION_PHY_REG
588 + csindex * 4, ®_data);
589 printf("%d,", (reg_data & 0x3f));
590 ddr3_tip_bus_read(dev_num, if_id,
591 ACCESS_TYPE_UNICAST, bus_id,
593 READ_CENTRALIZATION_PHY_REG
594 + csindex * 4, ®_data);
595 printf("%d,", (reg_data & 0x1f));
597 ddr3_tip_bus_read(dev_num, if_id,
598 ACCESS_TYPE_UNICAST, bus_id,
602 printf("%d,", (reg_data & 0x7));
604 /* Need to add the Read Function from device */
607 for (idx = 0; idx < 11; idx++) {
608 ddr3_tip_bus_read(dev_num, if_id,
610 bus_id, DDR_PHY_DATA,
614 printf("%d,", (reg_data & 0x3f));
617 for (idx = 0; idx < 11; idx++) {
618 ddr3_tip_bus_read(dev_num, if_id,
620 bus_id, DDR_PHY_DATA,
624 printf("%d,", (reg_data & 0x3f));
627 for (idx = 0; idx < 11; idx++) {
628 ddr3_tip_bus_read(dev_num, if_id,
630 bus_id, DDR_PHY_DATA,
634 printf("%d,", (reg_data & 0x3f));
645 * Register XSB information
647 int ddr3_tip_register_xsb_info(u32 dev_num, struct hws_xsb_info *xsb_info_table)
649 memcpy(&xsb_info[dev_num], xsb_info_table, sizeof(struct hws_xsb_info));
656 int read_adll_value(u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
657 int reg_addr, u32 mask)
660 u32 if_id = 0, bus_id = 0;
662 struct hws_topology_map *tm = ddr3_get_topology_map();
665 * multi CS support - reg_addr is calucalated in calling function
668 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
669 VALIDATE_ACTIVE(tm->if_act_mask, if_id);
670 for (bus_id = 0; bus_id < tm->num_of_bus_per_interface;
672 VALIDATE_ACTIVE(tm->bus_act_mask, bus_id);
673 CHECK_STATUS(ddr3_tip_bus_read(dev_num, if_id,
676 DDR_PHY_DATA, reg_addr,
679 tm->num_of_bus_per_interface + bus_id] =
690 int write_adll_value(u32 pup_values[MAX_INTERFACE_NUM * MAX_BUS_NUM],
693 u32 if_id = 0, bus_id = 0;
694 u32 dev_num = 0, data;
695 struct hws_topology_map *tm = ddr3_get_topology_map();
698 * multi CS support - reg_addr is calucalated in calling function
701 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
702 VALIDATE_ACTIVE(tm->if_act_mask, if_id);
703 for (bus_id = 0; bus_id < tm->num_of_bus_per_interface;
705 VALIDATE_ACTIVE(tm->bus_act_mask, bus_id);
706 data = pup_values[if_id *
707 tm->num_of_bus_per_interface +
709 CHECK_STATUS(ddr3_tip_bus_write(dev_num,
713 bus_id, DDR_PHY_DATA,
721 #ifndef EXCLUDE_SWITCH_DEBUG
722 u32 rl_version = 1; /* 0 - old RL machine */
723 struct hws_tip_config_func_db config_func_info[HWS_MAX_DEVICE_NUM];
724 u32 start_xsb_offset = 0;
727 u8 is_dfs_disabled = 0;
728 u32 default_centrlization_value = 0x12;
730 u32 activate_select_before_run_alg = 1, activate_deselect_after_run_alg = 1,
731 rl_test = 0, reset_read_fifo = 0;
733 u32 ctrl_sweepres[ADLL_LENGTH][MAX_INTERFACE_NUM][MAX_BUS_NUM];
734 u32 ctrl_adll[MAX_CS_NUM * MAX_INTERFACE_NUM * MAX_BUS_NUM];
736 0, 4, 8, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
739 u32 xsb_test_table[][8] = {
740 {0x00000000, 0x11111111, 0x22222222, 0x33333333, 0x44444444, 0x55555555,
741 0x66666666, 0x77777777},
742 {0x88888888, 0x99999999, 0xaaaaaaaa, 0xbbbbbbbb, 0xcccccccc, 0xdddddddd,
743 0xeeeeeeee, 0xffffffff},
744 {0x00000000, 0xffffffff, 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
745 0x00000000, 0xffffffff},
746 {0x00000000, 0xffffffff, 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
747 0x00000000, 0xffffffff},
748 {0x00000000, 0xffffffff, 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
749 0x00000000, 0xffffffff},
750 {0x00000000, 0xffffffff, 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
751 0x00000000, 0xffffffff},
752 {0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000, 0x00000000,
753 0xffffffff, 0xffffffff},
754 {0x00000000, 0x00000000, 0x00000000, 0xffffffff, 0x00000000, 0x00000000,
755 0x00000000, 0x00000000},
756 {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00000000, 0xffffffff,
757 0xffffffff, 0xffffffff}
760 static int ddr3_tip_access_atr(u32 dev_num, u32 flag_id, u32 value, u32 **ptr);
762 int ddr3_tip_print_adll(void)
764 u32 bus_cnt = 0, if_id, data_p1, data_p2, ui_data3, dev_num = 0;
765 struct hws_topology_map *tm = ddr3_get_topology_map();
767 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
768 VALIDATE_ACTIVE(tm->if_act_mask, if_id);
769 for (bus_cnt = 0; bus_cnt < GET_TOPOLOGY_NUM_OF_BUSES();
771 VALIDATE_ACTIVE(tm->bus_act_mask, bus_cnt);
772 CHECK_STATUS(ddr3_tip_bus_read
774 ACCESS_TYPE_UNICAST, bus_cnt,
775 DDR_PHY_DATA, 0x1, &data_p1));
776 CHECK_STATUS(ddr3_tip_bus_read
777 (dev_num, if_id, ACCESS_TYPE_UNICAST,
778 bus_cnt, DDR_PHY_DATA, 0x2, &data_p2));
779 CHECK_STATUS(ddr3_tip_bus_read
780 (dev_num, if_id, ACCESS_TYPE_UNICAST,
781 bus_cnt, DDR_PHY_DATA, 0x3, &ui_data3));
782 DEBUG_TRAINING_IP(DEBUG_LEVEL_TRACE,
783 (" IF %d bus_cnt %d phy_reg_1_data 0x%x phy_reg_2_data 0x%x phy_reg_3_data 0x%x\n",
784 if_id, bus_cnt, data_p1, data_p2,
793 * Set attribute value
795 int ddr3_tip_set_atr(u32 dev_num, u32 flag_id, u32 value)
798 u32 *ptr_flag = NULL;
800 ret = ddr3_tip_access_atr(dev_num, flag_id, value, &ptr_flag);
801 if (ptr_flag != NULL) {
802 printf("ddr3_tip_set_atr Flag ID 0x%x value is set to 0x%x (was 0x%x)\n",
803 flag_id, value, *ptr_flag);
806 printf("ddr3_tip_set_atr Flag ID 0x%x value is set to 0x%x\n",
816 static int ddr3_tip_access_atr(u32 dev_num, u32 flag_id, u32 value, u32 **ptr)
818 u32 tmp_val = 0, if_id = 0, pup_id = 0;
819 struct hws_topology_map *tm = ddr3_get_topology_map();
825 *ptr = (u32 *)&(tm->if_act_mask);
829 *ptr = (u32 *)&mask_tune_func;
833 *ptr = (u32 *)&low_freq;
837 *ptr = (u32 *)&medium_freq;
841 *ptr = (u32 *)&generic_init_controller;
845 *ptr = (u32 *)&rl_version;
849 *ptr = (u32 *)&start_xsb_offset;
853 *ptr = (u32 *)&is_rl_old;
857 *ptr = (u32 *)&is_freq_old;
861 *ptr = (u32 *)&is_dfs_disabled;
865 *ptr = (u32 *)&is_pll_before_init;
869 *ptr = (u32 *)&is_adll_calib_before_init;
871 #ifdef STATIC_ALGO_SUPPORT
873 *ptr = (u32 *)&(silicon_delay[0]);
877 *ptr = (u32 *)&wl_debug_delay;
881 *ptr = (u32 *)&is_tune_result;
885 *ptr = (u32 *)&is_validate_window_per_if;
889 *ptr = (u32 *)&is_validate_window_per_pup;
893 *ptr = (u32 *)&sweep_cnt;
897 *ptr = (u32 *)&is_bist_reset_bit;
901 *ptr = (u32 *)&is_dfs_in_init;
905 *ptr = (u32 *)&p_finger;
909 *ptr = (u32 *)&n_finger;
913 *ptr = (u32 *)&init_freq;
917 *ptr = (u32 *)&(freq_val[DDR_FREQ_LOW_FREQ]);
921 *ptr = (u32 *)&start_pattern;
925 *ptr = (u32 *)&end_pattern;
929 *ptr = (u32 *)&phy_reg0_val;
933 *ptr = (u32 *)&phy_reg1_val;
937 *ptr = (u32 *)&phy_reg2_val;
941 *ptr = (u32 *)&phy_reg3_val;
945 *ptr = (u32 *)&sweep_pattern;
949 *ptr = (u32 *)&is_rzq6;
953 *ptr = (u32 *)&znri_data_phy_val;
957 *ptr = (u32 *)&zpri_data_phy_val;
961 *ptr = (u32 *)&finger_test;
965 *ptr = (u32 *)&n_finger_start;
969 *ptr = (u32 *)&n_finger_end;
973 *ptr = (u32 *)&p_finger_start;
977 *ptr = (u32 *)&p_finger_end;
981 *ptr = (u32 *)&p_finger_step;
985 *ptr = (u32 *)&n_finger_step;
989 *ptr = (u32 *)&znri_ctrl_phy_val;
993 *ptr = (u32 *)&zpri_ctrl_phy_val;
997 *ptr = (u32 *)&is_reg_dump;
1001 *ptr = (u32 *)&vref;
1005 *ptr = (u32 *)&mode2_t;
1009 *ptr = (u32 *)&xsb_validate_type;
1013 *ptr = (u32 *)&xsb_validation_base_address;
1017 *ptr = (u32 *)&activate_select_before_run_alg;
1021 *ptr = (u32 *)&activate_deselect_after_run_alg;
1025 *ptr = (u32 *)&odt_additional;
1029 *ptr = (u32 *)&debug_mode;
1033 *ptr = (u32 *)&pbs_pattern;
1037 *ptr = (u32 *)&delay_enable;
1041 *ptr = (u32 *)&ck_delay;
1045 *ptr = (u32 *)&ck_delay_16;
1049 *ptr = (u32 *)&ca_delay;
1053 *ptr = (u32 *)&debug_dunit;
1057 debug_acc = (int)value;
1061 debug_training = (u8)value;
1065 debug_training_bist = (u8)value;
1069 debug_centralization = (u8)value;
1073 debug_training_ip = (u8)value;
1077 debug_leveling = (u8)value;
1081 debug_pbs = (u8)value;
1085 debug_training_static = (u8)value;
1089 debug_training_access = (u8)value;
1093 *ptr = &start_pattern;
1097 *ptr = &end_pattern;
1101 if ((flag_id >= 0x200) && (flag_id < 0x210)) {
1102 if_id = flag_id - 0x200;
1103 *ptr = (u32 *)&(tm->interface_params
1104 [if_id].memory_freq);
1105 } else if ((flag_id >= 0x210) && (flag_id < 0x220)) {
1106 if_id = flag_id - 0x210;
1107 *ptr = (u32 *)&(tm->interface_params
1108 [if_id].speed_bin_index);
1109 } else if ((flag_id >= 0x220) && (flag_id < 0x230)) {
1110 if_id = flag_id - 0x220;
1111 *ptr = (u32 *)&(tm->interface_params
1113 } else if ((flag_id >= 0x230) && (flag_id < 0x240)) {
1114 if_id = flag_id - 0x230;
1115 *ptr = (u32 *)&(tm->interface_params
1116 [if_id].memory_size);
1117 } else if ((flag_id >= 0x240) && (flag_id < 0x250)) {
1118 if_id = flag_id - 0x240;
1119 *ptr = (u32 *)&(tm->interface_params
1121 } else if ((flag_id >= 0x250) && (flag_id < 0x260)) {
1122 if_id = flag_id - 0x250;
1123 *ptr = (u32 *)&(tm->interface_params
1125 } else if ((flag_id >= 0x270) && (flag_id < 0x2cf)) {
1126 if_id = (flag_id - 0x270) / MAX_BUS_NUM;
1127 pup_id = (flag_id - 0x270) % MAX_BUS_NUM;
1128 *ptr = (u32 *)&(tm->interface_params[if_id].
1129 as_bus_params[pup_id].is_ck_swap);
1130 } else if ((flag_id >= 0x2d0) && (flag_id < 0x32f)) {
1131 if_id = (flag_id - 0x2d0) / MAX_BUS_NUM;
1132 pup_id = (flag_id - 0x2d0) % MAX_BUS_NUM;
1133 *ptr = (u32 *)&(tm->interface_params[if_id].
1134 as_bus_params[pup_id].is_dqs_swap);
1135 } else if ((flag_id >= 0x330) && (flag_id < 0x38f)) {
1136 if_id = (flag_id - 0x330) / MAX_BUS_NUM;
1137 pup_id = (flag_id - 0x330) % MAX_BUS_NUM;
1138 *ptr = (u32 *)&(tm->interface_params[if_id].
1139 as_bus_params[pup_id].cs_bitmask);
1140 } else if ((flag_id >= 0x390) && (flag_id < 0x3ef)) {
1141 if_id = (flag_id - 0x390) / MAX_BUS_NUM;
1142 pup_id = (flag_id - 0x390) % MAX_BUS_NUM;
1143 *ptr = (u32 *)&(tm->interface_params
1144 [if_id].as_bus_params
1145 [pup_id].mirror_enable_bitmask);
1146 } else if ((flag_id >= 0x500) && (flag_id <= 0x50f)) {
1147 tmp_val = flag_id - 0x320;
1148 *ptr = (u32 *)&(clamp_tbl[tmp_val]);
1150 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
1151 ("flag_id out of boundary %d\n",
1153 return MV_BAD_PARAM;
1160 #ifndef EXCLUDE_SWITCH_DEBUG
1164 int print_adll(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM])
1167 struct hws_topology_map *tm = ddr3_get_topology_map();
1169 for (j = 0; j < tm->num_of_bus_per_interface; j++) {
1170 VALIDATE_ACTIVE(tm->bus_act_mask, j);
1171 for (i = 0; i < MAX_INTERFACE_NUM; i++) {
1173 adll[i * tm->num_of_bus_per_interface + j]);
1182 /* byte_index - only byte 0, 1, 2, or 3, oxff - test all bytes */
1183 static u32 ddr3_tip_compare(u32 if_id, u32 *p_src, u32 *p_dst,
1186 u32 burst_cnt = 0, addr_offset, i_id;
1191 0xff) ? (u32) 0xffffffff : (u32) (0xff << (byte_index * 8));
1192 for (burst_cnt = 0; burst_cnt < EXT_ACCESS_BURST_LENGTH; burst_cnt++) {
1193 if ((p_src[burst_cnt] & addr_offset) !=
1194 (p_dst[burst_cnt] & addr_offset))
1198 if (b_is_fail == 1) {
1199 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
1200 ("IF %d exp: ", if_id));
1201 for (i_id = 0; i_id <= MAX_INTERFACE_NUM - 1; i_id++) {
1202 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
1203 ("0x%8x ", p_src[i_id]));
1205 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
1206 ("\n_i_f %d rcv: ", if_id));
1207 for (i_id = 0; i_id <= MAX_INTERFACE_NUM - 1; i_id++) {
1208 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR,
1209 ("(0x%8x ", p_dst[i_id]));
1211 DEBUG_TRAINING_IP(DEBUG_LEVEL_ERROR, ("\n "));
1217 /* test_type = 0-tx , 1-rx */
1218 int ddr3_tip_sweep_test(u32 dev_num, u32 test_type,
1219 u32 mem_addr, u32 is_modify_adll,
1220 u32 start_if, u32 end_if, u32 startpup, u32 endpup)
1222 u32 bus_cnt = 0, adll_val = 0, if_id, ui_prev_adll, ui_mask_bit,
1223 end_adll, start_adll;
1225 struct hws_topology_map *tm = ddr3_get_topology_map();
1227 if (test_type == 0) {
1231 end_adll = ui_mask_bit;
1236 end_adll = ui_mask_bit;
1239 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
1240 ("==============================\n"));
1241 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO,
1242 ("Test type %d (0-tx, 1-rx)\n", test_type));
1244 for (if_id = start_if; if_id <= end_if; if_id++) {
1245 VALIDATE_ACTIVE(tm->if_act_mask, if_id);
1246 for (bus_cnt = startpup; bus_cnt < endpup; bus_cnt++) {
1247 CHECK_STATUS(ddr3_tip_bus_read
1248 (dev_num, if_id, ACCESS_TYPE_UNICAST,
1249 bus_cnt, DDR_PHY_DATA, reg_addr,
1252 for (adll_val = start_adll; adll_val <= end_adll;
1254 if (is_modify_adll == 1) {
1255 CHECK_STATUS(ddr3_tip_bus_read_modify_write
1257 ACCESS_TYPE_UNICAST,
1259 DDR_PHY_DATA, reg_addr,
1260 adll_val, ui_mask_bit));
1263 if (is_modify_adll == 1) {
1264 CHECK_STATUS(ddr3_tip_bus_write
1265 (dev_num, ACCESS_TYPE_UNICAST,
1266 if_id, ACCESS_TYPE_UNICAST,
1267 bus_cnt, DDR_PHY_DATA, reg_addr,
1270 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("\n"));
1272 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("\n"));
1278 #ifndef EXCLUDE_SWITCH_DEBUG
1282 int ddr3_tip_run_sweep_test(int dev_num, u32 repeat_num, u32 direction,
1285 u32 pup = 0, start_pup = 0, end_pup = 0;
1287 u32 res[MAX_INTERFACE_NUM] = { 0 };
1290 int reg = (direction == 0) ? WRITE_CENTRALIZATION_PHY_REG :
1291 READ_CENTRALIZATION_PHY_REG;
1292 enum hws_access_type pup_access;
1294 u32 max_cs = hws_ddr3_tip_max_cs_get();
1295 struct hws_topology_map *tm = ddr3_get_topology_map();
1300 end_pup = tm->num_of_bus_per_interface - 1;
1301 pup_access = ACCESS_TYPE_UNICAST;
1305 pup_access = ACCESS_TYPE_MULTICAST;
1308 for (cs = 0; cs < max_cs; cs++) {
1309 for (adll = 0; adll < ADLL_LENGTH; adll++) {
1311 if_id <= MAX_INTERFACE_NUM - 1;
1316 for (pup = start_pup; pup <= end_pup; pup++) {
1317 ctrl_sweepres[adll][if_id][pup] =
1323 for (adll = 0; adll < (MAX_INTERFACE_NUM * MAX_BUS_NUM); adll++)
1324 ctrl_adll[adll] = 0;
1325 /* Save DQS value(after algorithm run) */
1326 read_adll_value(ctrl_adll,
1327 (reg + (cs * CS_REGISTER_ADDR_OFFSET)),
1331 * Sweep ADLL from 0:31 on all I/F on all Pup and perform
1332 * BIST on each stage.
1334 for (pup = start_pup; pup <= end_pup; pup++) {
1335 for (adll = 0; adll < ADLL_LENGTH; adll++) {
1337 (direction == 0) ? (adll * 2) : adll;
1338 CHECK_STATUS(ddr3_tip_bus_write
1339 (dev_num, ACCESS_TYPE_MULTICAST, 0,
1340 pup_access, pup, DDR_PHY_DATA,
1341 reg + CS_REG_VALUE(cs),
1343 hws_ddr3_run_bist(dev_num, sweep_pattern, res,
1345 /* ddr3_tip_reset_fifo_ptr(dev_num); */
1347 if_id <= MAX_INTERFACE_NUM - 1;
1352 ctrl_sweepres[adll][if_id][pup]
1358 ACCESS_TYPE_UNICAST,
1360 ACCESS_TYPE_UNICAST,
1363 reg + CS_REG_VALUE(cs),
1366 tm->num_of_bus_per_interface
1372 printf("Final, CS %d,%s, Sweep, Result, Adll,", cs,
1373 ((direction == 0) ? "TX" : "RX"));
1374 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
1375 VALIDATE_ACTIVE(tm->if_act_mask, if_id);
1377 for (pup = start_pup; pup <= end_pup; pup++) {
1378 VALIDATE_ACTIVE(tm->bus_act_mask, pup);
1379 printf("I/F%d-PHY%d , ", if_id, pup);
1382 printf("I/F%d , ", if_id);
1387 for (adll = 0; adll < ADLL_LENGTH; adll++) {
1388 adll_value = (direction == 0) ? (adll * 2) : adll;
1389 printf("Final,%s, Sweep, Result, %d ,",
1390 ((direction == 0) ? "TX" : "RX"), adll_value);
1393 if_id <= MAX_INTERFACE_NUM - 1;
1395 VALIDATE_ACTIVE(tm->if_act_mask, if_id);
1396 for (pup = start_pup; pup <= end_pup; pup++) {
1398 ctrl_sweepres[adll][if_id]
1406 * Write back to the phy the Rx DQS value, we store in
1409 write_adll_value(ctrl_adll,
1410 (reg + cs * CS_REGISTER_ADDR_OFFSET));
1411 /* print adll results */
1412 read_adll_value(ctrl_adll, (reg + cs * CS_REGISTER_ADDR_OFFSET),
1414 printf("%s, DQS, ADLL,,,", (direction == 0) ? "Tx" : "Rx");
1415 print_adll(dev_num, ctrl_adll);
1417 ddr3_tip_reset_fifo_ptr(dev_num);
1422 void print_topology(struct hws_topology_map *topology_db)
1426 printf("\tinterface_mask: 0x%x\n", topology_db->if_act_mask);
1427 printf("\tNum Bus: %d\n", topology_db->num_of_bus_per_interface);
1428 printf("\tbus_act_mask: 0x%x\n", topology_db->bus_act_mask);
1430 for (ui = 0; ui < MAX_INTERFACE_NUM; ui++) {
1431 VALIDATE_ACTIVE(topology_db->if_act_mask, ui);
1432 printf("\n\tInterface ID: %d\n", ui);
1433 printf("\t\tDDR Frequency: %s\n",
1434 convert_freq(topology_db->
1435 interface_params[ui].memory_freq));
1436 printf("\t\tSpeed_bin: %d\n",
1437 topology_db->interface_params[ui].speed_bin_index);
1438 printf("\t\tBus_width: %d\n",
1439 (4 << topology_db->interface_params[ui].bus_width));
1440 printf("\t\tMem_size: %s\n",
1441 convert_mem_size(topology_db->
1442 interface_params[ui].memory_size));
1443 printf("\t\tCAS-WL: %d\n",
1444 topology_db->interface_params[ui].cas_wl);
1445 printf("\t\tCAS-L: %d\n",
1446 topology_db->interface_params[ui].cas_l);
1447 printf("\t\tTemperature: %d\n",
1448 topology_db->interface_params[ui].interface_temp);
1450 for (uj = 0; uj < 4; uj++) {
1451 printf("\t\tBus %d parameters- CS Mask: 0x%x\t", uj,
1452 topology_db->interface_params[ui].
1453 as_bus_params[uj].cs_bitmask);
1454 printf("Mirror: 0x%x\t",
1455 topology_db->interface_params[ui].
1456 as_bus_params[uj].mirror_enable_bitmask);
1457 printf("DQS Swap is %s \t",
1459 interface_params[ui].as_bus_params[uj].
1460 is_dqs_swap == 1) ? "enabled" : "disabled");
1461 printf("Ck Swap:%s\t",
1463 interface_params[ui].as_bus_params[uj].
1464 is_ck_swap == 1) ? "enabled" : "disabled");
1472 * Execute XSB Test transaction (rd/wr/both)
1474 int run_xsb_test(u32 dev_num, u32 mem_addr, u32 write_type,
1475 u32 read_type, u32 burst_length)
1477 u32 seq = 0, if_id = 0, addr, cnt;
1478 int ret = MV_OK, ret_tmp;
1479 u32 data_read[MAX_INTERFACE_NUM];
1480 struct hws_topology_map *tm = ddr3_get_topology_map();
1482 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
1483 VALIDATE_ACTIVE(tm->if_act_mask, if_id);
1485 for (cnt = 0; cnt <= burst_length; cnt++) {
1486 seq = (seq + 1) % 8;
1487 if (write_type != 0) {
1488 CHECK_STATUS(ddr3_tip_ext_write
1489 (dev_num, if_id, addr, 1,
1490 xsb_test_table[seq]));
1492 if (read_type != 0) {
1493 CHECK_STATUS(ddr3_tip_ext_read
1494 (dev_num, if_id, addr, 1,
1497 if ((read_type != 0) && (write_type != 0)) {
1499 ddr3_tip_compare(if_id,
1500 xsb_test_table[seq],
1503 addr += (EXT_ACCESS_BURST_LENGTH * 4);
1504 ret = (ret != MV_OK) ? ret : ret_tmp;
1512 #else /*EXCLUDE_SWITCH_DEBUG */
1514 u32 rl_version = 1; /* 0 - old RL machine */
1516 u32 start_xsb_offset = 0;
1517 u8 cs_mask_reg[] = {
1518 0, 4, 8, 12, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
1521 int run_xsb_test(u32 dev_num, u32 mem_addr, u32 write_type,
1522 u32 read_type, u32 burst_length)