git.sur5r.net Git - u-boot/blob - drivers/ddr/marvell/a38x/ddr3_init.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) Marvell International Ltd. and its affiliates
   4  */
   5
   6 #include <common.h>
   7 #include <i2c.h>
   8 #include <spl.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/cpu.h>
  11 #include <asm/arch/soc.h>
  12
  13 #include "ddr3_init.h"
  14
  15 #include "../../../../arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h"
  16
  17 static struct dlb_config ddr3_dlb_config_table[] = {
  18         {REG_STATIC_DRAM_DLB_CONTROL, 0x2000005c},
  19         {DLB_BUS_OPTIMIZATION_WEIGHTS_REG, 0x00880000},
  20         {DLB_AGING_REGISTER, 0x0f7f007f},
  21         {DLB_EVICTION_CONTROL_REG, 0x0000129f},
  22         {DLB_EVICTION_TIMERS_REGISTER_REG, 0x00ff0000},
  23         {DLB_BUS_WEIGHTS_DIFF_CS, 0x04030802},
  24         {DLB_BUS_WEIGHTS_DIFF_BG, 0x00000a02},
  25         {DLB_BUS_WEIGHTS_SAME_BG, 0x09000a01},
  26         {DLB_BUS_WEIGHTS_RD_WR, 0x00020005},
  27         {DLB_BUS_WEIGHTS_ATTR_SYS_PRIO, 0x00060f10},
  28         {DLB_MAIN_QUEUE_MAP, 0x00000543},
  29         {DLB_LINE_SPLIT, 0x00000000},
  30         {DLB_USER_COMMAND_REG, 0x00000000},
  31         {0x0, 0x0}
  32 };
  33
  34 static struct dlb_config ddr3_dlb_config_table_a0[] = {
  35         {REG_STATIC_DRAM_DLB_CONTROL, 0x2000005c},
  36         {DLB_BUS_OPTIMIZATION_WEIGHTS_REG, 0x00880000},
  37         {DLB_AGING_REGISTER, 0x0f7f007f},
  38         {DLB_EVICTION_CONTROL_REG, 0x0000129f},
  39         {DLB_EVICTION_TIMERS_REGISTER_REG, 0x00ff0000},
  40         {DLB_BUS_WEIGHTS_DIFF_CS, 0x04030802},
  41         {DLB_BUS_WEIGHTS_DIFF_BG, 0x00000a02},
  42         {DLB_BUS_WEIGHTS_SAME_BG, 0x09000a01},
  43         {DLB_BUS_WEIGHTS_RD_WR, 0x00020005},
  44         {DLB_BUS_WEIGHTS_ATTR_SYS_PRIO, 0x00060f10},
  45         {DLB_MAIN_QUEUE_MAP, 0x00000543},
  46         {DLB_LINE_SPLIT, 0x00000000},
  47         {DLB_USER_COMMAND_REG, 0x00000000},
  48         {0x0, 0x0}
  49 };
  50
  51 #if defined(CONFIG_ARMADA_38X)
  52 struct dram_modes {
  53         char *mode_name;
  54         u8 cpu_freq;
  55         u8 fab_freq;
  56         u8 chip_id;
  57         u8 chip_board_rev;
  58         struct reg_data *regs;
  59 };
  60
  61 struct dram_modes ddr_modes[] = {
  62 #ifdef SUPPORT_STATIC_DUNIT_CONFIG
  63         /* Conf name, CPUFreq, Fab_freq, Chip ID, Chip/Board, MC regs*/
  64 #ifdef CONFIG_CUSTOMER_BOARD_SUPPORT
  65         {"a38x_customer_0_800", DDR_FREQ_800, 0, 0x0, A38X_CUSTOMER_BOARD_ID0,
  66          ddr3_customer_800},
  67         {"a38x_customer_1_800", DDR_FREQ_800, 0, 0x0, A38X_CUSTOMER_BOARD_ID1,
  68          ddr3_customer_800},
  69 #else
  70         {"a38x_533", DDR_FREQ_533, 0, 0x0, MARVELL_BOARD, ddr3_a38x_533},
  71         {"a38x_667", DDR_FREQ_667, 0, 0x0, MARVELL_BOARD, ddr3_a38x_667},
  72         {"a38x_800", DDR_FREQ_800, 0, 0x0, MARVELL_BOARD, ddr3_a38x_800},
  73         {"a38x_933", DDR_FREQ_933, 0, 0x0, MARVELL_BOARD, ddr3_a38x_933},
  74 #endif
  75 #endif
  76 };
  77 #endif /* defined(CONFIG_ARMADA_38X) */
  78
  79 /* Translates topology map definitions to real memory size in bits */
  80 u32 mem_size[] = {
  81         ADDR_SIZE_512MB, ADDR_SIZE_1GB, ADDR_SIZE_2GB, ADDR_SIZE_4GB,
  82         ADDR_SIZE_8GB
  83 };
  84
  85 static char *ddr_type = "DDR3";
  86
  87 /*
  88  * Set 1 to use dynamic DUNIT configuration,
  89  * set 0 (supported for A380 and AC3) to configure DUNIT in values set by
  90  * ddr3_tip_init_specific_reg_config
  91  */
  92 u8 generic_init_controller = 1;
  93
  94 #ifdef SUPPORT_STATIC_DUNIT_CONFIG
  95 static u32 ddr3_get_static_ddr_mode(void);
  96 #endif
  97 static int ddr3_hws_tune_training_params(u8 dev_num);
  98
  99 /* device revision */
 100 #define DEV_VERSION_ID_REG              0x1823c
 101 #define REVISON_ID_OFFS                 8
 102 #define REVISON_ID_MASK                 0xf00
 103
 104 /* A38x revisions */
 105 #define MV_88F68XX_Z1_ID                0x0
 106 #define MV_88F68XX_A0_ID                0x4
 107 /* A39x revisions */
 108 #define MV_88F69XX_Z1_ID                0x2
 109
 110 /*
 111  * sys_env_dlb_config_ptr_get
 112  *
 113  * DESCRIPTION: defines pointer to to DLB COnfiguration table
 114  *
 115  * INPUT: none
 116  *
 117  * OUTPUT: pointer to DLB COnfiguration table
 118  *
 119  * RETURN:
 120  *       returns pointer to DLB COnfiguration table
 121  */
 122 struct dlb_config *sys_env_dlb_config_ptr_get(void)
 123 {
 124 #ifdef CONFIG_ARMADA_39X
 125         return &ddr3_dlb_config_table_a0[0];
 126 #else
 127         if (sys_env_device_rev_get() == MV_88F68XX_A0_ID)
 128                 return &ddr3_dlb_config_table_a0[0];
 129         else
 130                 return &ddr3_dlb_config_table[0];
 131 #endif
 132 }
 133
 134 /*
 135  * sys_env_get_cs_ena_from_reg
 136  *
 137  * DESCRIPTION: Get bit mask of enabled CS
 138  *
 139  * INPUT: None
 140  *
 141  * OUTPUT: None
 142  *
 143  * RETURN:
 144  *       Bit mask of enabled CS, 1 if only CS0 enabled,
 145  *       3 if both CS0 and CS1 enabled
 146  */
 147 u32 sys_env_get_cs_ena_from_reg(void)
 148 {
 149         return reg_read(REG_DDR3_RANK_CTRL_ADDR) &
 150                 REG_DDR3_RANK_CTRL_CS_ENA_MASK;
 151 }
 152
 153 static void ddr3_restore_and_set_final_windows(u32 *win)
 154 {
 155         u32 win_ctrl_reg, num_of_win_regs;
 156         u32 cs_ena = sys_env_get_cs_ena_from_reg();
 157         u32 ui;
 158
 159         win_ctrl_reg = REG_XBAR_WIN_4_CTRL_ADDR;
 160         num_of_win_regs = 16;
 161
 162         /* Return XBAR windows 4-7 or 16-19 init configuration */
 163         for (ui = 0; ui < num_of_win_regs; ui++)
 164                 reg_write((win_ctrl_reg + 0x4 * ui), win[ui]);
 165
 166         printf("%s Training Sequence - Switching XBAR Window to FastPath Window\n",
 167                ddr_type);
 168
 169 #if defined DYNAMIC_CS_SIZE_CONFIG
 170         if (ddr3_fast_path_dynamic_cs_size_config(cs_ena) != MV_OK)
 171                 printf("ddr3_fast_path_dynamic_cs_size_config FAILED\n");
 172 #else
 173         u32 reg, cs;
 174         reg = 0x1fffffe1;
 175         for (cs = 0; cs < MAX_CS; cs++) {
 176                 if (cs_ena & (1 << cs)) {
 177                         reg |= (cs << 2);
 178                         break;
 179                 }
 180         }
 181         /* Open fast path Window to - 0.5G */
 182         reg_write(REG_FASTPATH_WIN_0_CTRL_ADDR, reg);
 183 #endif
 184 }
 185
 186 static int ddr3_save_and_set_training_windows(u32 *win)
 187 {
 188         u32 cs_ena;
 189         u32 reg, tmp_count, cs, ui;
 190         u32 win_ctrl_reg, win_base_reg, win_remap_reg;
 191         u32 num_of_win_regs, win_jump_index;
 192         win_ctrl_reg = REG_XBAR_WIN_4_CTRL_ADDR;
 193         win_base_reg = REG_XBAR_WIN_4_BASE_ADDR;
 194         win_remap_reg = REG_XBAR_WIN_4_REMAP_ADDR;
 195         win_jump_index = 0x10;
 196         num_of_win_regs = 16;
 197         struct hws_topology_map *tm = ddr3_get_topology_map();
 198
 199 #ifdef DISABLE_L2_FILTERING_DURING_DDR_TRAINING
 200         /*
 201          * Disable L2 filtering during DDR training
 202          * (when Cross Bar window is open)
 203          */
 204         reg_write(ADDRESS_FILTERING_END_REGISTER, 0);
 205 #endif
 206
 207         cs_ena = tm->interface_params[0].as_bus_params[0].cs_bitmask;
 208
 209         /* Close XBAR Window 19 - Not needed */
 210         /* {0x000200e8}  -   Open Mbus Window - 2G */
 211         reg_write(REG_XBAR_WIN_19_CTRL_ADDR, 0);
 212
 213         /* Save XBAR Windows 4-19 init configurations */
 214         for (ui = 0; ui < num_of_win_regs; ui++)
 215                 win[ui] = reg_read(win_ctrl_reg + 0x4 * ui);
 216
 217         /* Open XBAR Windows 4-7 or 16-19 for other CS */
 218         reg = 0;
 219         tmp_count = 0;
 220         for (cs = 0; cs < MAX_CS; cs++) {
 221                 if (cs_ena & (1 << cs)) {
 222                         switch (cs) {
 223                         case 0:
 224                                 reg = 0x0e00;
 225                                 break;
 226                         case 1:
 227                                 reg = 0x0d00;
 228                                 break;
 229                         case 2:
 230                                 reg = 0x0b00;
 231                                 break;
 232                         case 3:
 233                                 reg = 0x0700;
 234                                 break;
 235                         }
 236                         reg |= (1 << 0);
 237                         reg |= (SDRAM_CS_SIZE & 0xffff0000);
 238
 239                         reg_write(win_ctrl_reg + win_jump_index * tmp_count,
 240                                   reg);
 241                         reg = (((SDRAM_CS_SIZE + 1) * (tmp_count)) &
 242                                0xffff0000);
 243                         reg_write(win_base_reg + win_jump_index * tmp_count,
 244                                   reg);
 245
 246                         if (win_remap_reg <= REG_XBAR_WIN_7_REMAP_ADDR)
 247                                 reg_write(win_remap_reg +
 248                                           win_jump_index * tmp_count, 0);
 249
 250                         tmp_count++;
 251                 }
 252         }
 253
 254         return MV_OK;
 255 }
 256
 257 /*
 258  * Name:     ddr3_init - Main DDR3 Init function
 259  * Desc:     This routine initialize the DDR3 MC and runs HW training.
 260  * Args:     None.
 261  * Notes:
 262  * Returns:  None.
 263  */
 264 int ddr3_init(void)
 265 {
 266         u32 reg = 0;
 267         u32 soc_num;
 268         int status;
 269         u32 win[16];
 270
 271         /* SoC/Board special Initializtions */
 272         /* Get version from internal library */
 273         ddr3_print_version();
 274
 275         /*Add sub_version string */
 276         DEBUG_INIT_C("", SUB_VERSION, 1);
 277
 278         /* Switching CPU to MRVL ID */
 279         soc_num = (reg_read(REG_SAMPLE_RESET_HIGH_ADDR) & SAR1_CPU_CORE_MASK) >>
 280                 SAR1_CPU_CORE_OFFSET;
 281         switch (soc_num) {
 282         case 0x3:
 283         case 0x1:
 284                 reg_bit_set(CPU_CONFIGURATION_REG(1), CPU_MRVL_ID_OFFSET);
 285         case 0x0:
 286                 reg_bit_set(CPU_CONFIGURATION_REG(0), CPU_MRVL_ID_OFFSET);
 287         default:
 288                 break;
 289         }
 290
 291         /*
 292          * Set DRAM Reset Mask in case detected GPIO indication of wakeup from
 293          * suspend i.e the DRAM values will not be overwritten / reset when
 294          * waking from suspend
 295          */
 296         if (sys_env_suspend_wakeup_check() ==
 297             SUSPEND_WAKEUP_ENABLED_GPIO_DETECTED) {
 298                 reg_bit_set(REG_SDRAM_INIT_CTRL_ADDR,
 299                             1 << REG_SDRAM_INIT_RESET_MASK_OFFS);
 300         }
 301
 302         /*
 303          * Stage 0 - Set board configuration
 304          */
 305
 306         /* Check if DRAM is already initialized  */
 307         if (reg_read(REG_BOOTROM_ROUTINE_ADDR) &
 308             (1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS)) {
 309                 printf("%s Training Sequence - 2nd boot - Skip\n", ddr_type);
 310                 return MV_OK;
 311         }
 312
 313         /*
 314          * Stage 1 - Dunit Setup
 315          */
 316
 317         /* Fix read ready phases for all SOC in reg 0x15c8 */
 318         reg = reg_read(REG_TRAINING_DEBUG_3_ADDR);
 319         reg &= ~(REG_TRAINING_DEBUG_3_MASK);
 320         reg |= 0x4;             /* Phase 0 */
 321         reg &= ~(REG_TRAINING_DEBUG_3_MASK << REG_TRAINING_DEBUG_3_OFFS);
 322         reg |= (0x4 << (1 * REG_TRAINING_DEBUG_3_OFFS));        /* Phase 1 */
 323         reg &= ~(REG_TRAINING_DEBUG_3_MASK << (3 * REG_TRAINING_DEBUG_3_OFFS));
 324         reg |= (0x6 << (3 * REG_TRAINING_DEBUG_3_OFFS));        /* Phase 3 */
 325         reg &= ~(REG_TRAINING_DEBUG_3_MASK << (4 * REG_TRAINING_DEBUG_3_OFFS));
 326         reg |= (0x6 << (4 * REG_TRAINING_DEBUG_3_OFFS));
 327         reg &= ~(REG_TRAINING_DEBUG_3_MASK << (5 * REG_TRAINING_DEBUG_3_OFFS));
 328         reg |= (0x6 << (5 * REG_TRAINING_DEBUG_3_OFFS));
 329         reg_write(REG_TRAINING_DEBUG_3_ADDR, reg);
 330
 331         /*
 332          * Axi_bresp_mode[8] = Compliant,
 333          * Axi_addr_decode_cntrl[11] = Internal,
 334          * Axi_data_bus_width[0] = 128bit
 335          * */
 336         /* 0x14a8 - AXI Control Register */
 337         reg_write(REG_DRAM_AXI_CTRL_ADDR, 0);
 338
 339         /*
 340          * Stage 2 - Training Values Setup
 341          */
 342         /* Set X-BAR windows for the training sequence */
 343         ddr3_save_and_set_training_windows(win);
 344
 345 #ifdef SUPPORT_STATIC_DUNIT_CONFIG
 346         /*
 347          * Load static controller configuration (in case dynamic/generic init
 348          * is not enabled
 349          */
 350         if (generic_init_controller == 0) {
 351                 ddr3_tip_init_specific_reg_config(0,
 352                                                   ddr_modes
 353                                                   [ddr3_get_static_ddr_mode
 354                                                    ()].regs);
 355         }
 356 #endif
 357
 358         /* Tune training algo paramteres */
 359         status = ddr3_hws_tune_training_params(0);
 360         if (MV_OK != status)
 361                 return status;
 362
 363         /* Set log level for training lib */
 364         ddr3_hws_set_log_level(DEBUG_BLOCK_ALL, DEBUG_LEVEL_ERROR);
 365
 366         /* Start New Training IP */
 367         status = ddr3_hws_hw_training();
 368         if (MV_OK != status) {
 369                 printf("%s Training Sequence - FAILED\n", ddr_type);
 370                 return status;
 371         }
 372
 373         /*
 374          * Stage 3 - Finish
 375          */
 376         /* Restore and set windows */
 377         ddr3_restore_and_set_final_windows(win);
 378
 379         /* Update DRAM init indication in bootROM register */
 380         reg = reg_read(REG_BOOTROM_ROUTINE_ADDR);
 381         reg_write(REG_BOOTROM_ROUTINE_ADDR,
 382                   reg | (1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS));
 383
 384         /* DLB config */
 385         ddr3_new_tip_dlb_config();
 386
 387 #if defined(ECC_SUPPORT)
 388         if (ddr3_if_ecc_enabled())
 389                 ddr3_new_tip_ecc_scrub();
 390 #endif
 391
 392         printf("%s Training Sequence - Ended Successfully\n", ddr_type);
 393
 394         return MV_OK;
 395 }
 396
 397 /*
 398  * Name:     ddr3_get_cpu_freq
 399  * Desc:     read S@R and return CPU frequency
 400  * Args:
 401  * Notes:
 402  * Returns:  required value
 403  */
 404 u32 ddr3_get_cpu_freq(void)
 405 {
 406         return ddr3_tip_get_init_freq();
 407 }
 408
 409 /*
 410  * Name:     ddr3_get_fab_opt
 411  * Desc:     read S@R and return CPU frequency
 412  * Args:
 413  * Notes:
 414  * Returns:  required value
 415  */
 416 u32 ddr3_get_fab_opt(void)
 417 {
 418         return 0;               /* No fabric */
 419 }
 420
 421 /*
 422  * Name:     ddr3_get_static_m_cValue - Init Memory controller with
 423  *           static parameters
 424  * Desc:     Use this routine to init the controller without the HW training
 425  *           procedure.
 426  *           User must provide compatible header file with registers data.
 427  * Args:     None.
 428  * Notes:
 429  * Returns:  None.
 430  */
 431 u32 ddr3_get_static_mc_value(u32 reg_addr, u32 offset1, u32 mask1,
 432                              u32 offset2, u32 mask2)
 433 {
 434         u32 reg, temp;
 435
 436         reg = reg_read(reg_addr);
 437
 438         temp = (reg >> offset1) & mask1;
 439         if (mask2)
 440                 temp |= (reg >> offset2) & mask2;
 441
 442         return temp;
 443 }
 444
 445 /*
 446  * Name:     ddr3_get_static_ddr_mode - Init Memory controller with
 447  *           static parameters
 448  * Desc:     Use this routine to init the controller without the HW training
 449  *           procedure.
 450  *           User must provide compatible header file with registers data.
 451  * Args:     None.
 452  * Notes:
 453  * Returns:  None.
 454  */
 455 u32 ddr3_get_static_ddr_mode(void)
 456 {
 457         u32 chip_board_rev, i;
 458         u32 size;
 459
 460         /* Valid only for A380 only, MSYS using dynamic controller config */
 461 #ifdef CONFIG_CUSTOMER_BOARD_SUPPORT
 462         /*
 463          * Customer boards select DDR mode according to
 464          * board ID & Sample@Reset
 465          */
 466         chip_board_rev = mv_board_id_get();
 467 #else
 468         /* Marvell boards select DDR mode according to Sample@Reset only */
 469         chip_board_rev = MARVELL_BOARD;
 470 #endif
 471
 472         size = ARRAY_SIZE(ddr_modes);
 473         for (i = 0; i < size; i++) {
 474                 if ((ddr3_get_cpu_freq() == ddr_modes[i].cpu_freq) &&
 475                     (ddr3_get_fab_opt() == ddr_modes[i].fab_freq) &&
 476                     (chip_board_rev == ddr_modes[i].chip_board_rev))
 477                         return i;
 478         }
 479
 480         DEBUG_INIT_S("\n*** Error: ddr3_get_static_ddr_mode: No match for requested DDR mode. ***\n\n");
 481
 482         return 0;
 483 }
 484
 485 /******************************************************************************
 486  * Name:     ddr3_get_cs_num_from_reg
 487  * Desc:
 488  * Args:
 489  * Notes:
 490  * Returns:
 491  */
 492 u32 ddr3_get_cs_num_from_reg(void)
 493 {
 494         u32 cs_ena = sys_env_get_cs_ena_from_reg();
 495         u32 cs_count = 0;
 496         u32 cs;
 497
 498         for (cs = 0; cs < MAX_CS; cs++) {
 499                 if (cs_ena & (1 << cs))
 500                         cs_count++;
 501         }
 502
 503         return cs_count;
 504 }
 505
 506 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps)
 507 {
 508         u32 tmp, hclk = 200;
 509
 510         switch (freq_mode) {
 511         case 4:
 512                 tmp = 1;        /* DDR_400; */
 513                 hclk = 200;
 514                 break;
 515         case 0x8:
 516                 tmp = 1;        /* DDR_666; */
 517                 hclk = 333;
 518                 break;
 519         case 0xc:
 520                 tmp = 1;        /* DDR_800; */
 521                 hclk = 400;
 522                 break;
 523         default:
 524                 *ddr_freq = 0;
 525                 *hclk_ps = 0;
 526                 break;
 527         }
 528
 529         *ddr_freq = tmp;                /* DDR freq define */
 530         *hclk_ps = 1000000 / hclk;      /* values are 1/HCLK in ps */
 531
 532         return;
 533 }
 534
 535 void ddr3_new_tip_dlb_config(void)
 536 {
 537         u32 reg, i = 0;
 538         struct dlb_config *config_table_ptr = sys_env_dlb_config_ptr_get();
 539
 540         /* Write the configuration */
 541         while (config_table_ptr[i].reg_addr != 0) {
 542                 reg_write(config_table_ptr[i].reg_addr,
 543                           config_table_ptr[i].reg_data);
 544                 i++;
 545         }
 546
 547         /* Enable DLB */
 548         reg = reg_read(REG_STATIC_DRAM_DLB_CONTROL);
 549         reg |= DLB_ENABLE | DLB_WRITE_COALESING | DLB_AXI_PREFETCH_EN |
 550                 DLB_MBUS_PREFETCH_EN | PREFETCH_N_LN_SZ_TR;
 551         reg_write(REG_STATIC_DRAM_DLB_CONTROL, reg);
 552 }
 553
 554 int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena)
 555 {
 556         u32 reg, cs;
 557         u32 mem_total_size = 0;
 558         u32 cs_mem_size = 0;
 559         u32 mem_total_size_c, cs_mem_size_c;
 560
 561 #ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE
 562         u32 physical_mem_size;
 563         u32 max_mem_size = DEVICE_MAX_DRAM_ADDRESS_SIZE;
 564         struct hws_topology_map *tm = ddr3_get_topology_map();
 565 #endif
 566
 567         /* Open fast path windows */
 568         for (cs = 0; cs < MAX_CS; cs++) {
 569                 if (cs_ena & (1 << cs)) {
 570                         /* get CS size */
 571                         if (ddr3_calc_mem_cs_size(cs, &cs_mem_size) != MV_OK)
 572                                 return MV_FAIL;
 573
 574 #ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE
 575                         /*
 576                          * if number of address pins doesn't allow to use max
 577                          * mem size that is defined in topology
 578                          * mem size is defined by DEVICE_MAX_DRAM_ADDRESS_SIZE
 579                          */
 580                         physical_mem_size = mem_size
 581                                 [tm->interface_params[0].memory_size];
 582
 583                         if (ddr3_get_device_width(cs) == 16) {
 584                                 /*
 585                                  * 16bit mem device can be twice more - no need
 586                                  * in less significant pin
 587                                  */
 588                                 max_mem_size = DEVICE_MAX_DRAM_ADDRESS_SIZE * 2;
 589                         }
 590
 591                         if (physical_mem_size > max_mem_size) {
 592                                 cs_mem_size = max_mem_size *
 593                                         (ddr3_get_bus_width() /
 594                                          ddr3_get_device_width(cs));
 595                                 printf("Updated Physical Mem size is from 0x%x to %x\n",
 596                                        physical_mem_size,
 597                                        DEVICE_MAX_DRAM_ADDRESS_SIZE);
 598                         }
 599 #endif
 600
 601                         /* set fast path window control for the cs */
 602                         reg = 0xffffe1;
 603                         reg |= (cs << 2);
 604                         reg |= (cs_mem_size - 1) & 0xffff0000;
 605                         /*Open fast path Window */
 606                         reg_write(REG_FASTPATH_WIN_CTRL_ADDR(cs), reg);
 607
 608                         /* Set fast path window base address for the cs */
 609                         reg = ((cs_mem_size) * cs) & 0xffff0000;
 610                         /* Set base address */
 611                         reg_write(REG_FASTPATH_WIN_BASE_ADDR(cs), reg);
 612
 613                         /*
 614                          * Since memory size may be bigger than 4G the summ may
 615                          * be more than 32 bit word,
 616                          * so to estimate the result divide mem_total_size and
 617                          * cs_mem_size by 0x10000 (it is equal to >> 16)
 618                          */
 619                         mem_total_size_c = mem_total_size >> 16;
 620                         cs_mem_size_c = cs_mem_size >> 16;
 621                         /* if the sum less than 2 G - calculate the value */
 622                         if (mem_total_size_c + cs_mem_size_c < 0x10000)
 623                                 mem_total_size += cs_mem_size;
 624                         else    /* put max possible size */
 625                                 mem_total_size = L2_FILTER_FOR_MAX_MEMORY_SIZE;
 626                 }
 627         }
 628
 629         /* Set L2 filtering to Max Memory size */
 630         reg_write(ADDRESS_FILTERING_END_REGISTER, mem_total_size);
 631
 632         return MV_OK;
 633 }
 634
 635 u32 ddr3_get_bus_width(void)
 636 {
 637         u32 bus_width;
 638
 639         bus_width = (reg_read(REG_SDRAM_CONFIG_ADDR) & 0x8000) >>
 640                 REG_SDRAM_CONFIG_WIDTH_OFFS;
 641
 642         return (bus_width == 0) ? 16 : 32;
 643 }
 644
 645 u32 ddr3_get_device_width(u32 cs)
 646 {
 647         u32 device_width;
 648
 649         device_width = (reg_read(REG_SDRAM_ADDRESS_CTRL_ADDR) &
 650                         (0x3 << (REG_SDRAM_ADDRESS_CTRL_STRUCT_OFFS * cs))) >>
 651                 (REG_SDRAM_ADDRESS_CTRL_STRUCT_OFFS * cs);
 652
 653         return (device_width == 0) ? 8 : 16;
 654 }
 655
 656 static int ddr3_get_device_size(u32 cs)
 657 {
 658         u32 device_size_low, device_size_high, device_size;
 659         u32 data, cs_low_offset, cs_high_offset;
 660
 661         cs_low_offset = REG_SDRAM_ADDRESS_SIZE_OFFS + cs * 4;
 662         cs_high_offset = REG_SDRAM_ADDRESS_SIZE_OFFS +
 663                 REG_SDRAM_ADDRESS_SIZE_HIGH_OFFS + cs;
 664
 665         data = reg_read(REG_SDRAM_ADDRESS_CTRL_ADDR);
 666         device_size_low = (data >> cs_low_offset) & 0x3;
 667         device_size_high = (data >> cs_high_offset) & 0x1;
 668
 669         device_size = device_size_low | (device_size_high << 2);
 670
 671         switch (device_size) {
 672         case 0:
 673                 return 2048;
 674         case 2:
 675                 return 512;
 676         case 3:
 677                 return 1024;
 678         case 4:
 679                 return 4096;
 680         case 5:
 681                 return 8192;
 682         case 1:
 683         default:
 684                 DEBUG_INIT_C("Error: Wrong device size of Cs: ", cs, 1);
 685                 /*
 686                  * Small value will give wrong emem size in
 687                  * ddr3_calc_mem_cs_size
 688                  */
 689                 return 0;
 690         }
 691 }
 692
 693 int ddr3_calc_mem_cs_size(u32 cs, u32 *cs_size)
 694 {
 695         int cs_mem_size;
 696
 697         /* Calculate in GiB */
 698         cs_mem_size = ((ddr3_get_bus_width() / ddr3_get_device_width(cs)) *
 699                        ddr3_get_device_size(cs)) / 8;
 700
 701         /*
 702          * Multiple controller bus width, 2x for 64 bit
 703          * (SoC controller may be 32 or 64 bit,
 704          * so bit 15 in 0x1400, that means if whole bus used or only half,
 705          * have a differnt meaning
 706          */
 707         cs_mem_size *= DDR_CONTROLLER_BUS_WIDTH_MULTIPLIER;
 708
 709         if (!cs_mem_size || (cs_mem_size == 64) || (cs_mem_size == 4096)) {
 710                 DEBUG_INIT_C("Error: Wrong Memory size of Cs: ", cs, 1);
 711                 return MV_BAD_VALUE;
 712         }
 713
 714         *cs_size = cs_mem_size << 20;
 715         return MV_OK;
 716 }
 717
 718 /*
 719  * Name:     ddr3_hws_tune_training_params
 720  * Desc:
 721  * Args:
 722  * Notes: Tune internal training params
 723  * Returns:
 724  */
 725 static int ddr3_hws_tune_training_params(u8 dev_num)
 726 {
 727         struct tune_train_params params;
 728         int status;
 729
 730         /* NOTE: do not remove any field initilization */
 731         params.ck_delay = TUNE_TRAINING_PARAMS_CK_DELAY;
 732         params.ck_delay_16 = TUNE_TRAINING_PARAMS_CK_DELAY_16;
 733         params.p_finger = TUNE_TRAINING_PARAMS_PFINGER;
 734         params.n_finger = TUNE_TRAINING_PARAMS_NFINGER;
 735         params.phy_reg3_val = TUNE_TRAINING_PARAMS_PHYREG3VAL;
 736
 737         status = ddr3_tip_tune_training_params(dev_num, &params);
 738         if (MV_OK != status) {
 739                 printf("%s Training Sequence - FAILED\n", ddr_type);
 740                 return status;
 741         }
 742
 743         return MV_OK;
 744 }