1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) Marvell International Ltd. and its affiliates
10 #include <asm/arch/cpu.h>
11 #include <asm/arch/soc.h>
13 #include "ddr3_init.h"
15 #include "../../../../arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h"
17 static struct dlb_config ddr3_dlb_config_table[] = {
18 {REG_STATIC_DRAM_DLB_CONTROL, 0x2000005c},
19 {DLB_BUS_OPTIMIZATION_WEIGHTS_REG, 0x00880000},
20 {DLB_AGING_REGISTER, 0x0f7f007f},
21 {DLB_EVICTION_CONTROL_REG, 0x0000129f},
22 {DLB_EVICTION_TIMERS_REGISTER_REG, 0x00ff0000},
23 {DLB_BUS_WEIGHTS_DIFF_CS, 0x04030802},
24 {DLB_BUS_WEIGHTS_DIFF_BG, 0x00000a02},
25 {DLB_BUS_WEIGHTS_SAME_BG, 0x09000a01},
26 {DLB_BUS_WEIGHTS_RD_WR, 0x00020005},
27 {DLB_BUS_WEIGHTS_ATTR_SYS_PRIO, 0x00060f10},
28 {DLB_MAIN_QUEUE_MAP, 0x00000543},
29 {DLB_LINE_SPLIT, 0x00000000},
30 {DLB_USER_COMMAND_REG, 0x00000000},
34 static struct dlb_config ddr3_dlb_config_table_a0[] = {
35 {REG_STATIC_DRAM_DLB_CONTROL, 0x2000005c},
36 {DLB_BUS_OPTIMIZATION_WEIGHTS_REG, 0x00880000},
37 {DLB_AGING_REGISTER, 0x0f7f007f},
38 {DLB_EVICTION_CONTROL_REG, 0x0000129f},
39 {DLB_EVICTION_TIMERS_REGISTER_REG, 0x00ff0000},
40 {DLB_BUS_WEIGHTS_DIFF_CS, 0x04030802},
41 {DLB_BUS_WEIGHTS_DIFF_BG, 0x00000a02},
42 {DLB_BUS_WEIGHTS_SAME_BG, 0x09000a01},
43 {DLB_BUS_WEIGHTS_RD_WR, 0x00020005},
44 {DLB_BUS_WEIGHTS_ATTR_SYS_PRIO, 0x00060f10},
45 {DLB_MAIN_QUEUE_MAP, 0x00000543},
46 {DLB_LINE_SPLIT, 0x00000000},
47 {DLB_USER_COMMAND_REG, 0x00000000},
51 #if defined(CONFIG_ARMADA_38X)
58 struct reg_data *regs;
61 struct dram_modes ddr_modes[] = {
63 #endif /* defined(CONFIG_ARMADA_38X) */
65 /* Translates topology map definitions to real memory size in bits */
67 ADDR_SIZE_512MB, ADDR_SIZE_1GB, ADDR_SIZE_2GB, ADDR_SIZE_4GB,
71 static char *ddr_type = "DDR3";
74 * Set 1 to use dynamic DUNIT configuration,
75 * set 0 (supported for A380 and AC3) to configure DUNIT in values set by
76 * ddr3_tip_init_specific_reg_config
78 u8 generic_init_controller = 1;
80 static int ddr3_hws_tune_training_params(u8 dev_num);
83 #define DEV_VERSION_ID_REG 0x1823c
84 #define REVISON_ID_OFFS 8
85 #define REVISON_ID_MASK 0xf00
88 #define MV_88F68XX_Z1_ID 0x0
89 #define MV_88F68XX_A0_ID 0x4
91 #define MV_88F69XX_Z1_ID 0x2
94 * sys_env_dlb_config_ptr_get
96 * DESCRIPTION: defines pointer to to DLB COnfiguration table
100 * OUTPUT: pointer to DLB COnfiguration table
103 * returns pointer to DLB COnfiguration table
105 struct dlb_config *sys_env_dlb_config_ptr_get(void)
107 #ifdef CONFIG_ARMADA_39X
108 return &ddr3_dlb_config_table_a0[0];
110 if (sys_env_device_rev_get() == MV_88F68XX_A0_ID)
111 return &ddr3_dlb_config_table_a0[0];
113 return &ddr3_dlb_config_table[0];
118 * sys_env_get_cs_ena_from_reg
120 * DESCRIPTION: Get bit mask of enabled CS
127 * Bit mask of enabled CS, 1 if only CS0 enabled,
128 * 3 if both CS0 and CS1 enabled
130 u32 sys_env_get_cs_ena_from_reg(void)
132 return reg_read(REG_DDR3_RANK_CTRL_ADDR) &
133 REG_DDR3_RANK_CTRL_CS_ENA_MASK;
136 static void ddr3_restore_and_set_final_windows(u32 *win)
138 u32 win_ctrl_reg, num_of_win_regs;
139 u32 cs_ena = sys_env_get_cs_ena_from_reg();
142 win_ctrl_reg = REG_XBAR_WIN_4_CTRL_ADDR;
143 num_of_win_regs = 16;
145 /* Return XBAR windows 4-7 or 16-19 init configuration */
146 for (ui = 0; ui < num_of_win_regs; ui++)
147 reg_write((win_ctrl_reg + 0x4 * ui), win[ui]);
149 printf("%s Training Sequence - Switching XBAR Window to FastPath Window\n",
152 #if defined DYNAMIC_CS_SIZE_CONFIG
153 if (ddr3_fast_path_dynamic_cs_size_config(cs_ena) != MV_OK)
154 printf("ddr3_fast_path_dynamic_cs_size_config FAILED\n");
158 for (cs = 0; cs < MAX_CS; cs++) {
159 if (cs_ena & (1 << cs)) {
164 /* Open fast path Window to - 0.5G */
165 reg_write(REG_FASTPATH_WIN_0_CTRL_ADDR, reg);
169 static int ddr3_save_and_set_training_windows(u32 *win)
172 u32 reg, tmp_count, cs, ui;
173 u32 win_ctrl_reg, win_base_reg, win_remap_reg;
174 u32 num_of_win_regs, win_jump_index;
175 win_ctrl_reg = REG_XBAR_WIN_4_CTRL_ADDR;
176 win_base_reg = REG_XBAR_WIN_4_BASE_ADDR;
177 win_remap_reg = REG_XBAR_WIN_4_REMAP_ADDR;
178 win_jump_index = 0x10;
179 num_of_win_regs = 16;
180 struct hws_topology_map *tm = ddr3_get_topology_map();
182 #ifdef DISABLE_L2_FILTERING_DURING_DDR_TRAINING
184 * Disable L2 filtering during DDR training
185 * (when Cross Bar window is open)
187 reg_write(ADDRESS_FILTERING_END_REGISTER, 0);
190 cs_ena = tm->interface_params[0].as_bus_params[0].cs_bitmask;
192 /* Close XBAR Window 19 - Not needed */
193 /* {0x000200e8} - Open Mbus Window - 2G */
194 reg_write(REG_XBAR_WIN_19_CTRL_ADDR, 0);
196 /* Save XBAR Windows 4-19 init configurations */
197 for (ui = 0; ui < num_of_win_regs; ui++)
198 win[ui] = reg_read(win_ctrl_reg + 0x4 * ui);
200 /* Open XBAR Windows 4-7 or 16-19 for other CS */
203 for (cs = 0; cs < MAX_CS; cs++) {
204 if (cs_ena & (1 << cs)) {
220 reg |= (SDRAM_CS_SIZE & 0xffff0000);
222 reg_write(win_ctrl_reg + win_jump_index * tmp_count,
224 reg = (((SDRAM_CS_SIZE + 1) * (tmp_count)) &
226 reg_write(win_base_reg + win_jump_index * tmp_count,
229 if (win_remap_reg <= REG_XBAR_WIN_7_REMAP_ADDR)
230 reg_write(win_remap_reg +
231 win_jump_index * tmp_count, 0);
241 * Name: ddr3_init - Main DDR3 Init function
242 * Desc: This routine initialize the DDR3 MC and runs HW training.
254 /* SoC/Board special Initializtions */
255 /* Get version from internal library */
256 ddr3_print_version();
258 /*Add sub_version string */
259 DEBUG_INIT_C("", SUB_VERSION, 1);
261 /* Switching CPU to MRVL ID */
262 soc_num = (reg_read(REG_SAMPLE_RESET_HIGH_ADDR) & SAR1_CPU_CORE_MASK) >>
263 SAR1_CPU_CORE_OFFSET;
267 reg_bit_set(CPU_CONFIGURATION_REG(1), CPU_MRVL_ID_OFFSET);
269 reg_bit_set(CPU_CONFIGURATION_REG(0), CPU_MRVL_ID_OFFSET);
275 * Set DRAM Reset Mask in case detected GPIO indication of wakeup from
276 * suspend i.e the DRAM values will not be overwritten / reset when
277 * waking from suspend
279 if (sys_env_suspend_wakeup_check() ==
280 SUSPEND_WAKEUP_ENABLED_GPIO_DETECTED) {
281 reg_bit_set(REG_SDRAM_INIT_CTRL_ADDR,
282 1 << REG_SDRAM_INIT_RESET_MASK_OFFS);
286 * Stage 0 - Set board configuration
289 /* Check if DRAM is already initialized */
290 if (reg_read(REG_BOOTROM_ROUTINE_ADDR) &
291 (1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS)) {
292 printf("%s Training Sequence - 2nd boot - Skip\n", ddr_type);
297 * Stage 1 - Dunit Setup
300 /* Fix read ready phases for all SOC in reg 0x15c8 */
301 reg = reg_read(REG_TRAINING_DEBUG_3_ADDR);
302 reg &= ~(REG_TRAINING_DEBUG_3_MASK);
303 reg |= 0x4; /* Phase 0 */
304 reg &= ~(REG_TRAINING_DEBUG_3_MASK << REG_TRAINING_DEBUG_3_OFFS);
305 reg |= (0x4 << (1 * REG_TRAINING_DEBUG_3_OFFS)); /* Phase 1 */
306 reg &= ~(REG_TRAINING_DEBUG_3_MASK << (3 * REG_TRAINING_DEBUG_3_OFFS));
307 reg |= (0x6 << (3 * REG_TRAINING_DEBUG_3_OFFS)); /* Phase 3 */
308 reg &= ~(REG_TRAINING_DEBUG_3_MASK << (4 * REG_TRAINING_DEBUG_3_OFFS));
309 reg |= (0x6 << (4 * REG_TRAINING_DEBUG_3_OFFS));
310 reg &= ~(REG_TRAINING_DEBUG_3_MASK << (5 * REG_TRAINING_DEBUG_3_OFFS));
311 reg |= (0x6 << (5 * REG_TRAINING_DEBUG_3_OFFS));
312 reg_write(REG_TRAINING_DEBUG_3_ADDR, reg);
315 * Axi_bresp_mode[8] = Compliant,
316 * Axi_addr_decode_cntrl[11] = Internal,
317 * Axi_data_bus_width[0] = 128bit
319 /* 0x14a8 - AXI Control Register */
320 reg_write(REG_DRAM_AXI_CTRL_ADDR, 0);
323 * Stage 2 - Training Values Setup
325 /* Set X-BAR windows for the training sequence */
326 ddr3_save_and_set_training_windows(win);
329 /* Tune training algo paramteres */
330 status = ddr3_hws_tune_training_params(0);
334 /* Set log level for training lib */
335 ddr3_hws_set_log_level(DEBUG_BLOCK_ALL, DEBUG_LEVEL_ERROR);
337 /* Start New Training IP */
338 status = ddr3_hws_hw_training();
339 if (MV_OK != status) {
340 printf("%s Training Sequence - FAILED\n", ddr_type);
347 /* Restore and set windows */
348 ddr3_restore_and_set_final_windows(win);
350 /* Update DRAM init indication in bootROM register */
351 reg = reg_read(REG_BOOTROM_ROUTINE_ADDR);
352 reg_write(REG_BOOTROM_ROUTINE_ADDR,
353 reg | (1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS));
356 ddr3_new_tip_dlb_config();
358 #if defined(ECC_SUPPORT)
359 if (ddr3_if_ecc_enabled())
360 ddr3_new_tip_ecc_scrub();
363 printf("%s Training Sequence - Ended Successfully\n", ddr_type);
369 * Name: ddr3_get_cpu_freq
370 * Desc: read S@R and return CPU frequency
373 * Returns: required value
375 u32 ddr3_get_cpu_freq(void)
377 return ddr3_tip_get_init_freq();
381 * Name: ddr3_get_fab_opt
382 * Desc: read S@R and return CPU frequency
385 * Returns: required value
387 u32 ddr3_get_fab_opt(void)
389 return 0; /* No fabric */
393 * Name: ddr3_get_static_m_cValue - Init Memory controller with
395 * Desc: Use this routine to init the controller without the HW training
397 * User must provide compatible header file with registers data.
402 u32 ddr3_get_static_mc_value(u32 reg_addr, u32 offset1, u32 mask1,
403 u32 offset2, u32 mask2)
407 reg = reg_read(reg_addr);
409 temp = (reg >> offset1) & mask1;
411 temp |= (reg >> offset2) & mask2;
417 * Name: ddr3_get_static_ddr_mode - Init Memory controller with
419 * Desc: Use this routine to init the controller without the HW training
421 * User must provide compatible header file with registers data.
426 u32 ddr3_get_static_ddr_mode(void)
428 u32 chip_board_rev, i;
431 /* Valid only for A380 only, MSYS using dynamic controller config */
432 #ifdef CONFIG_CUSTOMER_BOARD_SUPPORT
434 * Customer boards select DDR mode according to
435 * board ID & Sample@Reset
437 chip_board_rev = mv_board_id_get();
439 /* Marvell boards select DDR mode according to Sample@Reset only */
440 chip_board_rev = MARVELL_BOARD;
443 size = ARRAY_SIZE(ddr_modes);
444 for (i = 0; i < size; i++) {
445 if ((ddr3_get_cpu_freq() == ddr_modes[i].cpu_freq) &&
446 (ddr3_get_fab_opt() == ddr_modes[i].fab_freq) &&
447 (chip_board_rev == ddr_modes[i].chip_board_rev))
451 DEBUG_INIT_S("\n*** Error: ddr3_get_static_ddr_mode: No match for requested DDR mode. ***\n\n");
456 /******************************************************************************
457 * Name: ddr3_get_cs_num_from_reg
463 u32 ddr3_get_cs_num_from_reg(void)
465 u32 cs_ena = sys_env_get_cs_ena_from_reg();
469 for (cs = 0; cs < MAX_CS; cs++) {
470 if (cs_ena & (1 << cs))
477 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps)
483 tmp = 1; /* DDR_400; */
487 tmp = 1; /* DDR_666; */
491 tmp = 1; /* DDR_800; */
500 *ddr_freq = tmp; /* DDR freq define */
501 *hclk_ps = 1000000 / hclk; /* values are 1/HCLK in ps */
506 void ddr3_new_tip_dlb_config(void)
509 struct dlb_config *config_table_ptr = sys_env_dlb_config_ptr_get();
511 /* Write the configuration */
512 while (config_table_ptr[i].reg_addr != 0) {
513 reg_write(config_table_ptr[i].reg_addr,
514 config_table_ptr[i].reg_data);
519 reg = reg_read(REG_STATIC_DRAM_DLB_CONTROL);
520 reg |= DLB_ENABLE | DLB_WRITE_COALESING | DLB_AXI_PREFETCH_EN |
521 DLB_MBUS_PREFETCH_EN | PREFETCH_N_LN_SZ_TR;
522 reg_write(REG_STATIC_DRAM_DLB_CONTROL, reg);
525 int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena)
528 u32 mem_total_size = 0;
530 u32 mem_total_size_c, cs_mem_size_c;
532 #ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE
533 u32 physical_mem_size;
534 u32 max_mem_size = DEVICE_MAX_DRAM_ADDRESS_SIZE;
535 struct hws_topology_map *tm = ddr3_get_topology_map();
538 /* Open fast path windows */
539 for (cs = 0; cs < MAX_CS; cs++) {
540 if (cs_ena & (1 << cs)) {
542 if (ddr3_calc_mem_cs_size(cs, &cs_mem_size) != MV_OK)
545 #ifdef DEVICE_MAX_DRAM_ADDRESS_SIZE
547 * if number of address pins doesn't allow to use max
548 * mem size that is defined in topology
549 * mem size is defined by DEVICE_MAX_DRAM_ADDRESS_SIZE
551 physical_mem_size = mem_size
552 [tm->interface_params[0].memory_size];
554 if (ddr3_get_device_width(cs) == 16) {
556 * 16bit mem device can be twice more - no need
557 * in less significant pin
559 max_mem_size = DEVICE_MAX_DRAM_ADDRESS_SIZE * 2;
562 if (physical_mem_size > max_mem_size) {
563 cs_mem_size = max_mem_size *
564 (ddr3_get_bus_width() /
565 ddr3_get_device_width(cs));
566 printf("Updated Physical Mem size is from 0x%x to %x\n",
568 DEVICE_MAX_DRAM_ADDRESS_SIZE);
572 /* set fast path window control for the cs */
575 reg |= (cs_mem_size - 1) & 0xffff0000;
576 /*Open fast path Window */
577 reg_write(REG_FASTPATH_WIN_CTRL_ADDR(cs), reg);
579 /* Set fast path window base address for the cs */
580 reg = ((cs_mem_size) * cs) & 0xffff0000;
581 /* Set base address */
582 reg_write(REG_FASTPATH_WIN_BASE_ADDR(cs), reg);
585 * Since memory size may be bigger than 4G the summ may
586 * be more than 32 bit word,
587 * so to estimate the result divide mem_total_size and
588 * cs_mem_size by 0x10000 (it is equal to >> 16)
590 mem_total_size_c = mem_total_size >> 16;
591 cs_mem_size_c = cs_mem_size >> 16;
592 /* if the sum less than 2 G - calculate the value */
593 if (mem_total_size_c + cs_mem_size_c < 0x10000)
594 mem_total_size += cs_mem_size;
595 else /* put max possible size */
596 mem_total_size = L2_FILTER_FOR_MAX_MEMORY_SIZE;
600 /* Set L2 filtering to Max Memory size */
601 reg_write(ADDRESS_FILTERING_END_REGISTER, mem_total_size);
606 u32 ddr3_get_bus_width(void)
610 bus_width = (reg_read(REG_SDRAM_CONFIG_ADDR) & 0x8000) >>
611 REG_SDRAM_CONFIG_WIDTH_OFFS;
613 return (bus_width == 0) ? 16 : 32;
616 u32 ddr3_get_device_width(u32 cs)
620 device_width = (reg_read(REG_SDRAM_ADDRESS_CTRL_ADDR) &
621 (0x3 << (REG_SDRAM_ADDRESS_CTRL_STRUCT_OFFS * cs))) >>
622 (REG_SDRAM_ADDRESS_CTRL_STRUCT_OFFS * cs);
624 return (device_width == 0) ? 8 : 16;
627 static int ddr3_get_device_size(u32 cs)
629 u32 device_size_low, device_size_high, device_size;
630 u32 data, cs_low_offset, cs_high_offset;
632 cs_low_offset = REG_SDRAM_ADDRESS_SIZE_OFFS + cs * 4;
633 cs_high_offset = REG_SDRAM_ADDRESS_SIZE_OFFS +
634 REG_SDRAM_ADDRESS_SIZE_HIGH_OFFS + cs;
636 data = reg_read(REG_SDRAM_ADDRESS_CTRL_ADDR);
637 device_size_low = (data >> cs_low_offset) & 0x3;
638 device_size_high = (data >> cs_high_offset) & 0x1;
640 device_size = device_size_low | (device_size_high << 2);
642 switch (device_size) {
655 DEBUG_INIT_C("Error: Wrong device size of Cs: ", cs, 1);
657 * Small value will give wrong emem size in
658 * ddr3_calc_mem_cs_size
664 int ddr3_calc_mem_cs_size(u32 cs, u32 *cs_size)
668 /* Calculate in GiB */
669 cs_mem_size = ((ddr3_get_bus_width() / ddr3_get_device_width(cs)) *
670 ddr3_get_device_size(cs)) / 8;
673 * Multiple controller bus width, 2x for 64 bit
674 * (SoC controller may be 32 or 64 bit,
675 * so bit 15 in 0x1400, that means if whole bus used or only half,
676 * have a differnt meaning
678 cs_mem_size *= DDR_CONTROLLER_BUS_WIDTH_MULTIPLIER;
680 if (!cs_mem_size || (cs_mem_size == 64) || (cs_mem_size == 4096)) {
681 DEBUG_INIT_C("Error: Wrong Memory size of Cs: ", cs, 1);
685 *cs_size = cs_mem_size << 20;
690 * Name: ddr3_hws_tune_training_params
693 * Notes: Tune internal training params
696 static int ddr3_hws_tune_training_params(u8 dev_num)
698 struct tune_train_params params;
701 /* NOTE: do not remove any field initilization */
702 params.ck_delay = TUNE_TRAINING_PARAMS_CK_DELAY;
703 params.ck_delay_16 = TUNE_TRAINING_PARAMS_CK_DELAY_16;
704 params.p_finger = TUNE_TRAINING_PARAMS_PFINGER;
705 params.n_finger = TUNE_TRAINING_PARAMS_NFINGER;
706 params.phy_reg3_val = TUNE_TRAINING_PARAMS_PHYREG3VAL;
708 status = ddr3_tip_tune_training_params(dev_num, ¶ms);
709 if (MV_OK != status) {
710 printf("%s Training Sequence - FAILED\n", ddr_type);