1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) Marvell International Ltd. and its affiliates
7 #include "mv_ddr_common.h"
10 * Translates topology map definitions to real memory size in bits
11 * (per values in ddr3_training_ip_def.h)
21 static char *ddr_type = "DDR3";
24 * generic_init_controller controls D-unit configuration:
25 * '1' - dynamic D-unit configuration,
27 u8 generic_init_controller = 1;
29 static int mv_ddr_training_params_set(u8 dev_num);
32 * Name: ddr3_init - Main DDR3 Init function
33 * Desc: This routine initialize the DDR3 MC and runs HW training.
40 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
41 u32 octets_per_if_num;
43 int is_manual_cal_done;
45 /* Print mv_ddr version */
48 mv_ddr_pre_training_fixup();
50 /* SoC/Board special initializations */
51 mv_ddr_pre_training_soc_config(ddr_type);
53 /* Set log level for training library */
54 mv_ddr_user_log_level_set(DEBUG_BLOCK_ALL);
58 if (mv_ddr_topology_map_update() == NULL) {
59 printf("mv_ddr: failed to update topology\n");
63 if (mv_ddr_early_init2() != MV_OK)
66 /* Set training algorithm's parameters */
67 status = mv_ddr_training_params_set(0);
74 is_manual_cal_done = mv_ddr_manual_cal_do();
78 if (!is_manual_cal_done) {
82 status = ddr3_silicon_post_init();
83 if (MV_OK != status) {
84 printf("DDR3 Post Init - FAILED 0x%x\n", status);
88 /* PHY initialization (Training) */
89 status = hws_ddr3_tip_run_alg(0, ALGO_TYPE_DYNAMIC);
90 if (MV_OK != status) {
91 printf("%s Training Sequence - FAILED\n", ddr_type);
95 #if defined(CONFIG_PHY_STATIC_PRINT)
96 mv_ddr_phy_static_print();
99 /* Post MC/PHY initializations */
100 mv_ddr_post_training_soc_config(ddr_type);
102 mv_ddr_post_training_fixup();
104 octets_per_if_num = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
105 if (ddr3_if_ecc_enabled()) {
106 if (MV_DDR_IS_64BIT_DRAM_MODE(tm->bus_act_mask) ||
107 MV_DDR_IS_32BIT_IN_64BIT_DRAM_MODE(tm->bus_act_mask, octets_per_if_num))
108 mv_ddr_mem_scrubbing();
110 ddr3_new_tip_ecc_scrub();
113 printf("mv_ddr: completed successfully\n");
118 uint64_t mv_ddr_get_memory_size_per_cs_in_bits(void)
120 uint64_t memory_size_per_cs;
122 u32 bus_cnt, num_of_active_bus = 0;
123 u32 num_of_sub_phys_per_ddr_unit = 0;
125 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
127 u32 octets_per_if_num = ddr3_tip_dev_attr_get(DEV_NUM_0, MV_ATTR_OCTET_PER_INTERFACE);
129 /* count the number of active bus */
130 for (bus_cnt = 0; bus_cnt < octets_per_if_num - 1/* ignore ecc octet */; bus_cnt++) {
131 VALIDATE_BUS_ACTIVE(tm->bus_act_mask, bus_cnt);
135 /* calculate number of sub-phys per ddr unit */
136 if (tm->interface_params[0].bus_width/* supports only single interface */ == MV_DDR_DEV_WIDTH_16BIT)
137 num_of_sub_phys_per_ddr_unit = TWO_SUB_PHYS;
138 if (tm->interface_params[0].bus_width/* supports only single interface */ == MV_DDR_DEV_WIDTH_8BIT)
139 num_of_sub_phys_per_ddr_unit = SINGLE_SUB_PHY;
141 /* calculate dram size per cs */
142 memory_size_per_cs = (uint64_t)mem_size[tm->interface_params[0].memory_size] * (uint64_t)num_of_active_bus
143 / (uint64_t)num_of_sub_phys_per_ddr_unit * (uint64_t)MV_DDR_NUM_BITS_IN_BYTE;
145 return memory_size_per_cs;
148 uint64_t mv_ddr_get_total_memory_size_in_bits(void)
150 uint64_t total_memory_size = 0;
151 uint64_t memory_size_per_cs = 0;
153 /* get the number of cs */
154 u32 max_cs = ddr3_tip_max_cs_get(DEV_NUM_0);
156 memory_size_per_cs = mv_ddr_get_memory_size_per_cs_in_bits();
157 total_memory_size = (uint64_t)max_cs * memory_size_per_cs;
159 return total_memory_size;
162 int ddr3_if_ecc_enabled(void)
164 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
166 if (DDR3_IS_ECC_PUP4_MODE(tm->bus_act_mask) ||
167 DDR3_IS_ECC_PUP3_MODE(tm->bus_act_mask) ||
168 DDR3_IS_ECC_PUP8_MODE(tm->bus_act_mask))
175 * Name: mv_ddr_training_params_set
178 * Notes: sets internal training params
181 static int mv_ddr_training_params_set(u8 dev_num)
183 struct tune_train_params params;
185 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
189 CHECK_STATUS(ddr3_tip_get_first_active_if
190 (dev_num, tm->if_act_mask,
193 CHECK_STATUS(calc_cs_num(dev_num, if_id, &cs_num));
195 /* NOTE: do not remove any field initilization */
196 params.ck_delay = TUNE_TRAINING_PARAMS_CK_DELAY;
197 params.phy_reg3_val = TUNE_TRAINING_PARAMS_PHYREG3VAL;
198 params.g_zpri_data = TUNE_TRAINING_PARAMS_PRI_DATA;
199 params.g_znri_data = TUNE_TRAINING_PARAMS_NRI_DATA;
200 params.g_zpri_ctrl = TUNE_TRAINING_PARAMS_PRI_CTRL;
201 params.g_znri_ctrl = TUNE_TRAINING_PARAMS_NRI_CTRL;
202 params.g_znodt_data = TUNE_TRAINING_PARAMS_N_ODT_DATA;
203 params.g_zpodt_ctrl = TUNE_TRAINING_PARAMS_P_ODT_CTRL;
204 params.g_znodt_ctrl = TUNE_TRAINING_PARAMS_N_ODT_CTRL;
206 params.g_zpodt_data = TUNE_TRAINING_PARAMS_P_ODT_DATA;
207 params.g_dic = TUNE_TRAINING_PARAMS_DIC;
208 params.g_rtt_nom = TUNE_TRAINING_PARAMS_RTT_NOM;
210 params.g_rtt_wr = TUNE_TRAINING_PARAMS_RTT_WR_1CS;
211 params.g_odt_config = TUNE_TRAINING_PARAMS_ODT_CONFIG_1CS;
213 params.g_rtt_wr = TUNE_TRAINING_PARAMS_RTT_WR_2CS;
214 params.g_odt_config = TUNE_TRAINING_PARAMS_ODT_CONFIG_2CS;
217 status = ddr3_tip_tune_training_params(dev_num, ¶ms);
218 if (MV_OK != status) {
219 printf("%s Training Sequence - FAILED\n", ddr_type);