1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) Marvell International Ltd. and its affiliates
9 #if defined(CONFIG_ARMADA_38X)
10 #include "ddr3_a38x.h"
11 #include "ddr3_a38x_topology.h"
13 #include "ddr3_hws_hw_training.h"
14 #include "ddr3_hws_sil_training.h"
15 #include "ddr3_logging_def.h"
16 #include "ddr3_training_hw_algo.h"
17 #include "ddr3_training_ip.h"
18 #include "ddr3_training_ip_centralization.h"
19 #include "ddr3_training_ip_engine.h"
20 #include "ddr3_training_ip_flow.h"
21 #include "ddr3_training_ip_pbs.h"
22 #include "ddr3_training_ip_prv_if.h"
23 #include "ddr3_training_ip_static.h"
24 #include "ddr3_training_leveling.h"
28 * MV_DEBUG_INIT need to be defines, otherwise the output of the
29 * DDR2 training code is not complete and misleading
34 #define DEBUG_INIT_S(s) puts(s)
35 #define DEBUG_INIT_D(d, l) printf("%x", d)
36 #define DEBUG_INIT_D_10(d, l) printf("%d", d)
38 #define DEBUG_INIT_S(s)
39 #define DEBUG_INIT_D(d, l)
40 #define DEBUG_INIT_D_10(d, l)
43 #ifdef MV_DEBUG_INIT_FULL
44 #define DEBUG_INIT_FULL_S(s) puts(s)
45 #define DEBUG_INIT_FULL_D(d, l) printf("%x", d)
46 #define DEBUG_INIT_FULL_D_10(d, l) printf("%d", d)
47 #define DEBUG_WR_REG(reg, val) \
48 { DEBUG_INIT_S("Write Reg: 0x"); DEBUG_INIT_D((reg), 8); \
49 DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); }
50 #define DEBUG_RD_REG(reg, val) \
51 { DEBUG_INIT_S("Read Reg: 0x"); DEBUG_INIT_D((reg), 8); \
52 DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); }
54 #define DEBUG_INIT_FULL_S(s)
55 #define DEBUG_INIT_FULL_D(d, l)
56 #define DEBUG_INIT_FULL_D_10(d, l)
57 #define DEBUG_WR_REG(reg, val)
58 #define DEBUG_RD_REG(reg, val)
61 #define DEBUG_INIT_FULL_C(s, d, l) \
62 { DEBUG_INIT_FULL_S(s); \
63 DEBUG_INIT_FULL_D(d, l); \
64 DEBUG_INIT_FULL_S("\n"); }
65 #define DEBUG_INIT_C(s, d, l) \
66 { DEBUG_INIT_S(s); DEBUG_INIT_D(d, l); DEBUG_INIT_S("\n"); }
69 * Debug (Enable/Disable modules) and Error report
75 #define MV_DEBUG_DQS_RESULTS
85 #define MV_DEBUG_MAIN_FULL
86 #define MV_DEBUG_DFS_FULL
87 #define MV_DEBUG_DQS_FULL
88 #define MV_DEBUG_RL_FULL
89 #define MV_DEBUG_WL_FULL
92 #if defined(CONFIG_ARMADA_38X)
93 #include "ddr3_a38x.h"
94 #include "ddr3_a38x_topology.h"
97 /* The following is a list of Marvell status */
99 #define MV_OK (0x00) /* Operation succeeded */
100 #define MV_FAIL (0x01) /* Operation failed */
101 #define MV_BAD_VALUE (0x02) /* Illegal value (general) */
102 #define MV_OUT_OF_RANGE (0x03) /* The value is out of range */
103 #define MV_BAD_PARAM (0x04) /* Illegal parameter in function called */
104 #define MV_BAD_PTR (0x05) /* Illegal pointer value */
105 #define MV_BAD_SIZE (0x06) /* Illegal size */
106 #define MV_BAD_STATE (0x07) /* Illegal state of state machine */
107 #define MV_SET_ERROR (0x08) /* Set operation failed */
108 #define MV_GET_ERROR (0x09) /* Get operation failed */
109 #define MV_CREATE_ERROR (0x0a) /* Fail while creating an item */
110 #define MV_NOT_FOUND (0x0b) /* Item not found */
111 #define MV_NO_MORE (0x0c) /* No more items found */
112 #define MV_NO_SUCH (0x0d) /* No such item */
113 #define MV_TIMEOUT (0x0e) /* Time Out */
114 #define MV_NO_CHANGE (0x0f) /* Parameter(s) is already in this value */
115 #define MV_NOT_SUPPORTED (0x10) /* This request is not support */
116 #define MV_NOT_IMPLEMENTED (0x11) /* Request supported but not implemented*/
117 #define MV_NOT_INITIALIZED (0x12) /* The item is not initialized */
118 #define MV_NO_RESOURCE (0x13) /* Resource not available (memory ...) */
119 #define MV_FULL (0x14) /* Item is full (Queue or table etc...) */
120 #define MV_EMPTY (0x15) /* Item is empty (Queue or table etc...) */
121 #define MV_INIT_ERROR (0x16) /* Error occurred while INIT process */
122 #define MV_HW_ERROR (0x17) /* Hardware error */
123 #define MV_TX_ERROR (0x18) /* Transmit operation not succeeded */
124 #define MV_RX_ERROR (0x19) /* Recieve operation not succeeded */
125 #define MV_NOT_READY (0x1a) /* The other side is not ready yet */
126 #define MV_ALREADY_EXIST (0x1b) /* Tried to create existing item */
127 #define MV_OUT_OF_CPU_MEM (0x1c) /* Cpu memory allocation failed. */
128 #define MV_NOT_STARTED (0x1d) /* Not started yet */
129 #define MV_BUSY (0x1e) /* Item is busy. */
130 #define MV_TERMINATE (0x1f) /* Item terminates it's work. */
131 #define MV_NOT_ALIGNED (0x20) /* Wrong alignment */
132 #define MV_NOT_ALLOWED (0x21) /* Operation NOT allowed */
133 #define MV_WRITE_PROTECT (0x22) /* Write protected */
134 #define MV_INVALID (int)(-1)
136 /* For checking function return values */
137 #define CHECK_STATUS(orig_func) \
140 status = orig_func; \
141 if (MV_OK != status) \
153 extern u8 debug_training;
154 extern u8 is_reg_dump;
155 extern u8 generic_init_controller;
156 extern u32 freq_val[];
157 extern u32 is_pll_old;
158 extern struct cl_val_per_freq cas_latency_table[];
159 extern struct pattern_info pattern_table[];
160 extern struct cl_val_per_freq cas_write_latency_table[];
161 extern u8 debug_training;
162 extern u8 debug_centralization, debug_training_ip, debug_training_bist,
163 debug_pbs, debug_training_static, debug_leveling;
164 extern u32 pipe_multicast_mask;
165 extern struct hws_tip_config_func_db config_func_info[];
166 extern u8 cs_mask_reg[];
167 extern u8 twr_mask_table[];
168 extern u8 cl_mask_table[];
169 extern u8 cwl_mask_table[];
170 extern u16 rfc_table[];
171 extern u32 speed_bin_table_t_rc[];
172 extern u32 speed_bin_table_t_rcd_t_rp[];
173 extern u32 ck_delay, ck_delay_16;
175 extern u32 g_zpri_data;
176 extern u32 g_znri_data;
177 extern u32 g_zpri_ctrl;
178 extern u32 g_znri_ctrl;
179 extern u32 g_zpodt_data;
180 extern u32 g_znodt_data;
181 extern u32 g_zpodt_ctrl;
182 extern u32 g_znodt_ctrl;
184 extern u32 g_odt_config_2cs;
185 extern u32 g_odt_config_1cs;
186 extern u32 g_rtt_nom;
188 extern u8 debug_training_access;
189 extern u8 debug_training_a38x;
190 extern u32 first_active_if;
191 extern enum hws_ddr_freq init_freq;
192 extern u32 delay_enable, ck_delay, ck_delay_16, ca_delay;
193 extern u32 mask_tune_func;
194 extern u32 rl_version;
195 extern int rl_mid_freq_wa;
196 extern u8 calibration_update_control; /* 2 external only, 1 is internal only */
197 extern enum hws_ddr_freq medium_freq;
199 extern u32 ck_delay, ck_delay_16;
200 extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
201 extern u32 first_active_if;
202 extern u32 mask_tune_func;
203 extern u32 freq_val[];
204 extern enum hws_ddr_freq init_freq;
205 extern enum hws_ddr_freq low_freq;
206 extern enum hws_ddr_freq medium_freq;
207 extern u8 generic_init_controller;
208 extern enum auto_tune_stage training_stage;
209 extern u32 is_pll_before_init;
210 extern u32 is_adll_calib_before_init;
211 extern u32 is_dfs_in_init;
212 extern int wl_debug_delay;
213 extern u32 silicon_delay[HWS_MAX_DEVICE_NUM];
216 extern u32 freq_val[DDR_FREQ_LIMIT];
217 extern u32 start_pattern, end_pattern;
218 extern u32 phy_reg0_val;
219 extern u32 phy_reg1_val;
220 extern u32 phy_reg2_val;
221 extern u32 phy_reg3_val;
222 extern enum hws_pattern sweep_pattern;
223 extern enum hws_pattern pbs_pattern;
225 extern u32 znri_data_phy_val;
226 extern u32 zpri_data_phy_val;
227 extern u32 znri_ctrl_phy_val;
228 extern u32 zpri_ctrl_phy_val;
229 extern u8 debug_training_access;
230 extern u32 finger_test, p_finger_start, p_finger_end, n_finger_start,
231 n_finger_end, p_finger_step, n_finger_step;
233 extern u32 xsb_validate_type;
234 extern u32 xsb_validation_base_address;
235 extern u32 odt_additional;
236 extern u32 debug_mode;
237 extern u32 delay_enable;
239 extern u32 debug_dunit;
240 extern u32 clamp_tbl[];
241 extern u32 freq_mask[HWS_MAX_DEVICE_NUM][DDR_FREQ_LIMIT];
242 extern u32 start_pattern, end_pattern;
244 extern u32 maxt_poll_tries;
245 extern u32 is_bist_reset_bit;
246 extern u8 debug_training_bist;
248 extern u8 vref_window_size[MAX_INTERFACE_NUM][MAX_BUS_NUM];
249 extern u32 debug_mode;
250 extern u32 effective_cs;
251 extern int ddr3_tip_centr_skip_min_win_check;
252 extern u32 *dq_map_table;
253 extern enum auto_tune_stage training_stage;
254 extern u8 debug_centralization;
256 extern u32 delay_enable;
257 extern u32 start_pattern, end_pattern;
258 extern u32 freq_val[DDR_FREQ_LIMIT];
259 extern u8 debug_training_hw_alg;
260 extern enum auto_tune_stage training_stage;
262 extern u8 debug_training_ip;
263 extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
264 extern enum auto_tune_stage training_stage;
265 extern u32 effective_cs;
267 extern u8 debug_leveling;
268 extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
269 extern enum auto_tune_stage training_stage;
270 extern u32 rl_version;
271 extern struct cl_val_per_freq cas_latency_table[];
272 extern u32 start_xsb_offset;
273 extern u32 debug_mode;
274 extern u32 odt_config;
275 extern u32 effective_cs;
276 extern u32 phy_reg1_val;
279 extern u32 effective_cs;
280 extern u16 mask_results_dq_reg_map[];
281 extern enum hws_ddr_freq medium_freq;
282 extern u32 freq_val[];
283 extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
284 extern enum auto_tune_stage training_stage;
285 extern u32 debug_mode;
286 extern u32 *dq_map_table;
289 extern struct cl_val_per_freq cas_latency_table[];
290 extern u32 target_freq;
291 extern struct hws_tip_config_func_db config_func_info[HWS_MAX_DEVICE_NUM];
292 extern u32 clamp_tbl[];
293 extern u32 init_freq;
294 /* list of allowed frequency listed in order of enum hws_ddr_freq */
295 extern u32 freq_val[];
296 extern u8 debug_training_static;
297 extern u32 first_active_if;
300 int ddr3_tip_enable_init_sequence(u32 dev_num);
302 int ddr3_tip_init_a38x(u32 dev_num, u32 board_id);
304 int ddr3_hws_hw_training(void);
305 int ddr3_silicon_pre_init(void);
306 int ddr3_silicon_post_init(void);
307 int ddr3_post_run_alg(void);
308 int ddr3_if_ecc_enabled(void);
309 void ddr3_new_tip_ecc_scrub(void);
311 void ddr3_print_version(void);
312 void ddr3_new_tip_dlb_config(void);
313 struct hws_topology_map *ddr3_get_topology_map(void);
315 int ddr3_if_ecc_enabled(void);
316 int ddr3_tip_reg_write(u32 dev_num, u32 reg_addr, u32 data);
317 int ddr3_tip_reg_read(u32 dev_num, u32 reg_addr, u32 *data, u32 reg_mask);
318 int ddr3_silicon_get_ddr_target_freq(u32 *ddr_freq);
319 int ddr3_tip_a38x_get_freq_config(u8 dev_num, enum hws_ddr_freq freq,
320 struct hws_tip_freq_config_info
322 int ddr3_a38x_update_topology_map(u32 dev_num,
323 struct hws_topology_map *topology_map);
324 int ddr3_tip_a38x_get_init_freq(int dev_num, enum hws_ddr_freq *freq);
325 int ddr3_tip_a38x_get_medium_freq(int dev_num, enum hws_ddr_freq *freq);
326 int ddr3_tip_a38x_if_read(u8 dev_num, enum hws_access_type interface_access,
327 u32 if_id, u32 reg_addr, u32 *data, u32 mask);
328 int ddr3_tip_a38x_if_write(u8 dev_num, enum hws_access_type interface_access,
329 u32 if_id, u32 reg_addr, u32 data, u32 mask);
330 int ddr3_tip_a38x_get_device_info(u8 dev_num,
331 struct ddr3_device_info *info_ptr);
333 int ddr3_tip_init_a38x(u32 dev_num, u32 board_id);
335 int print_adll(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM]);
336 int ddr3_tip_restore_dunit_regs(u32 dev_num);
337 void print_topology(struct hws_topology_map *topology_db);
339 u32 mv_board_id_get(void);
341 int ddr3_load_topology_map(void);
342 int ddr3_tip_init_specific_reg_config(u32 dev_num,
343 struct reg_data *reg_config_arr);
344 u32 ddr3_tip_get_init_freq(void);
345 void ddr3_hws_set_log_level(enum ddr_lib_debug_block block, u8 level);
346 int ddr3_tip_tune_training_params(u32 dev_num,
347 struct tune_train_params *params);
348 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
349 int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena);
350 void ddr3_fast_path_static_cs_size_config(u32 cs_ena);
351 u32 ddr3_get_device_width(u32 cs);
352 u32 mv_board_id_index_get(u32 board_id);
353 u32 mv_board_id_get(void);
354 u32 ddr3_get_bus_width(void);
355 void ddr3_set_log_level(u32 n_log_level);
356 int ddr3_calc_mem_cs_size(u32 cs, u32 *cs_size);
358 int hws_ddr3_cs_base_adr_calc(u32 if_id, u32 cs, u32 *cs_base_addr);
360 int ddr3_tip_print_pbs_result(u32 dev_num, u32 cs_num, enum pbs_dir pbs_mode);
361 int ddr3_tip_clean_pbs_result(u32 dev_num, enum pbs_dir pbs_mode);
363 int ddr3_tip_static_round_trip_arr_build(u32 dev_num,
364 struct trip_delay_element *table_ptr,
365 int is_wl, u32 *round_trip_delay_arr);
367 u32 hws_ddr3_tip_max_cs_get(void);
370 * Accessor functions for the registers
372 static inline void reg_write(u32 addr, u32 val)
374 writel(val, INTER_REGS_BASE + addr);
377 static inline u32 reg_read(u32 addr)
379 return readl(INTER_REGS_BASE + addr);
382 static inline void reg_bit_set(u32 addr, u32 mask)
384 setbits_le32(INTER_REGS_BASE + addr, mask);
387 static inline void reg_bit_clr(u32 addr, u32 mask)
389 clrbits_le32(INTER_REGS_BASE + addr, mask);
392 #endif /* _DDR3_INIT_H */