2 * Copyright (C) Marvell International Ltd. and its affiliates
4 * SPDX-License-Identifier: GPL-2.0
10 #if defined(CONFIG_ARMADA_38X)
11 #include "ddr3_a38x.h"
12 #include "ddr3_a38x_mc_static.h"
13 #include "ddr3_a38x_topology.h"
15 #include "ddr3_hws_hw_training.h"
16 #include "ddr3_hws_sil_training.h"
17 #include "ddr3_logging_def.h"
18 #include "ddr3_training_hw_algo.h"
19 #include "ddr3_training_ip.h"
20 #include "ddr3_training_ip_centralization.h"
21 #include "ddr3_training_ip_engine.h"
22 #include "ddr3_training_ip_flow.h"
23 #include "ddr3_training_ip_pbs.h"
24 #include "ddr3_training_ip_prv_if.h"
25 #include "ddr3_training_ip_static.h"
26 #include "ddr3_training_leveling.h"
30 * MV_DEBUG_INIT need to be defines, otherwise the output of the
31 * DDR2 training code is not complete and misleading
36 #define DEBUG_INIT_S(s) puts(s)
37 #define DEBUG_INIT_D(d, l) printf("%x", d)
38 #define DEBUG_INIT_D_10(d, l) printf("%d", d)
40 #define DEBUG_INIT_S(s)
41 #define DEBUG_INIT_D(d, l)
42 #define DEBUG_INIT_D_10(d, l)
45 #ifdef MV_DEBUG_INIT_FULL
46 #define DEBUG_INIT_FULL_S(s) puts(s)
47 #define DEBUG_INIT_FULL_D(d, l) printf("%x", d)
48 #define DEBUG_INIT_FULL_D_10(d, l) printf("%d", d)
49 #define DEBUG_WR_REG(reg, val) \
50 { DEBUG_INIT_S("Write Reg: 0x"); DEBUG_INIT_D((reg), 8); \
51 DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); }
52 #define DEBUG_RD_REG(reg, val) \
53 { DEBUG_INIT_S("Read Reg: 0x"); DEBUG_INIT_D((reg), 8); \
54 DEBUG_INIT_S("= "); DEBUG_INIT_D((val), 8); DEBUG_INIT_S("\n"); }
56 #define DEBUG_INIT_FULL_S(s)
57 #define DEBUG_INIT_FULL_D(d, l)
58 #define DEBUG_INIT_FULL_D_10(d, l)
59 #define DEBUG_WR_REG(reg, val)
60 #define DEBUG_RD_REG(reg, val)
63 #define DEBUG_INIT_FULL_C(s, d, l) \
64 { DEBUG_INIT_FULL_S(s); \
65 DEBUG_INIT_FULL_D(d, l); \
66 DEBUG_INIT_FULL_S("\n"); }
67 #define DEBUG_INIT_C(s, d, l) \
68 { DEBUG_INIT_S(s); DEBUG_INIT_D(d, l); DEBUG_INIT_S("\n"); }
71 * Debug (Enable/Disable modules) and Error report
77 #define MV_DEBUG_DQS_RESULTS
87 #define MV_DEBUG_MAIN_FULL
88 #define MV_DEBUG_DFS_FULL
89 #define MV_DEBUG_DQS_FULL
90 #define MV_DEBUG_RL_FULL
91 #define MV_DEBUG_WL_FULL
94 #if defined(CONFIG_ARMADA_38X)
95 #include "ddr3_a38x.h"
96 #include "ddr3_a38x_topology.h"
99 /* The following is a list of Marvell status */
100 #define MV_ERROR (-1)
101 #define MV_OK (0x00) /* Operation succeeded */
102 #define MV_FAIL (0x01) /* Operation failed */
103 #define MV_BAD_VALUE (0x02) /* Illegal value (general) */
104 #define MV_OUT_OF_RANGE (0x03) /* The value is out of range */
105 #define MV_BAD_PARAM (0x04) /* Illegal parameter in function called */
106 #define MV_BAD_PTR (0x05) /* Illegal pointer value */
107 #define MV_BAD_SIZE (0x06) /* Illegal size */
108 #define MV_BAD_STATE (0x07) /* Illegal state of state machine */
109 #define MV_SET_ERROR (0x08) /* Set operation failed */
110 #define MV_GET_ERROR (0x09) /* Get operation failed */
111 #define MV_CREATE_ERROR (0x0a) /* Fail while creating an item */
112 #define MV_NOT_FOUND (0x0b) /* Item not found */
113 #define MV_NO_MORE (0x0c) /* No more items found */
114 #define MV_NO_SUCH (0x0d) /* No such item */
115 #define MV_TIMEOUT (0x0e) /* Time Out */
116 #define MV_NO_CHANGE (0x0f) /* Parameter(s) is already in this value */
117 #define MV_NOT_SUPPORTED (0x10) /* This request is not support */
118 #define MV_NOT_IMPLEMENTED (0x11) /* Request supported but not implemented*/
119 #define MV_NOT_INITIALIZED (0x12) /* The item is not initialized */
120 #define MV_NO_RESOURCE (0x13) /* Resource not available (memory ...) */
121 #define MV_FULL (0x14) /* Item is full (Queue or table etc...) */
122 #define MV_EMPTY (0x15) /* Item is empty (Queue or table etc...) */
123 #define MV_INIT_ERROR (0x16) /* Error occurred while INIT process */
124 #define MV_HW_ERROR (0x17) /* Hardware error */
125 #define MV_TX_ERROR (0x18) /* Transmit operation not succeeded */
126 #define MV_RX_ERROR (0x19) /* Recieve operation not succeeded */
127 #define MV_NOT_READY (0x1a) /* The other side is not ready yet */
128 #define MV_ALREADY_EXIST (0x1b) /* Tried to create existing item */
129 #define MV_OUT_OF_CPU_MEM (0x1c) /* Cpu memory allocation failed. */
130 #define MV_NOT_STARTED (0x1d) /* Not started yet */
131 #define MV_BUSY (0x1e) /* Item is busy. */
132 #define MV_TERMINATE (0x1f) /* Item terminates it's work. */
133 #define MV_NOT_ALIGNED (0x20) /* Wrong alignment */
134 #define MV_NOT_ALLOWED (0x21) /* Operation NOT allowed */
135 #define MV_WRITE_PROTECT (0x22) /* Write protected */
136 #define MV_INVALID (int)(-1)
138 /* For checking function return values */
139 #define CHECK_STATUS(orig_func) \
142 status = orig_func; \
143 if (MV_OK != status) \
155 extern u8 debug_training;
156 extern u8 is_reg_dump;
157 extern u8 generic_init_controller;
158 extern u32 freq_val[];
159 extern u32 is_pll_old;
160 extern struct cl_val_per_freq cas_latency_table[];
161 extern struct pattern_info pattern_table[];
162 extern struct cl_val_per_freq cas_write_latency_table[];
163 extern u8 debug_training;
164 extern u8 debug_centralization, debug_training_ip, debug_training_bist,
165 debug_pbs, debug_training_static, debug_leveling;
166 extern u32 pipe_multicast_mask;
167 extern struct hws_tip_config_func_db config_func_info[];
168 extern u8 cs_mask_reg[];
169 extern u8 twr_mask_table[];
170 extern u8 cl_mask_table[];
171 extern u8 cwl_mask_table[];
172 extern u16 rfc_table[];
173 extern u32 speed_bin_table_t_rc[];
174 extern u32 speed_bin_table_t_rcd_t_rp[];
175 extern u32 ck_delay, ck_delay_16;
177 extern u32 g_zpri_data;
178 extern u32 g_znri_data;
179 extern u32 g_zpri_ctrl;
180 extern u32 g_znri_ctrl;
181 extern u32 g_zpodt_data;
182 extern u32 g_znodt_data;
183 extern u32 g_zpodt_ctrl;
184 extern u32 g_znodt_ctrl;
186 extern u32 g_odt_config_2cs;
187 extern u32 g_odt_config_1cs;
188 extern u32 g_rtt_nom;
190 extern u8 debug_training_access;
191 extern u8 debug_training_a38x;
192 extern u32 first_active_if;
193 extern enum hws_ddr_freq init_freq;
194 extern u32 delay_enable, ck_delay, ck_delay_16, ca_delay;
195 extern u32 mask_tune_func;
196 extern u32 rl_version;
197 extern int rl_mid_freq_wa;
198 extern u8 calibration_update_control; /* 2 external only, 1 is internal only */
199 extern enum hws_ddr_freq medium_freq;
201 extern u32 ck_delay, ck_delay_16;
202 extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
203 extern u32 first_active_if;
204 extern u32 mask_tune_func;
205 extern u32 freq_val[];
206 extern enum hws_ddr_freq init_freq;
207 extern enum hws_ddr_freq low_freq;
208 extern enum hws_ddr_freq medium_freq;
209 extern u8 generic_init_controller;
210 extern enum auto_tune_stage training_stage;
211 extern u32 is_pll_before_init;
212 extern u32 is_adll_calib_before_init;
213 extern u32 is_dfs_in_init;
214 extern int wl_debug_delay;
215 extern u32 silicon_delay[HWS_MAX_DEVICE_NUM];
218 extern u32 freq_val[DDR_FREQ_LIMIT];
219 extern u32 start_pattern, end_pattern;
220 extern u32 phy_reg0_val;
221 extern u32 phy_reg1_val;
222 extern u32 phy_reg2_val;
223 extern u32 phy_reg3_val;
224 extern enum hws_pattern sweep_pattern;
225 extern enum hws_pattern pbs_pattern;
227 extern u32 znri_data_phy_val;
228 extern u32 zpri_data_phy_val;
229 extern u32 znri_ctrl_phy_val;
230 extern u32 zpri_ctrl_phy_val;
231 extern u8 debug_training_access;
232 extern u32 finger_test, p_finger_start, p_finger_end, n_finger_start,
233 n_finger_end, p_finger_step, n_finger_step;
235 extern u32 xsb_validate_type;
236 extern u32 xsb_validation_base_address;
237 extern u32 odt_additional;
238 extern u32 debug_mode;
239 extern u32 delay_enable;
241 extern u32 debug_dunit;
242 extern u32 clamp_tbl[];
243 extern u32 freq_mask[HWS_MAX_DEVICE_NUM][DDR_FREQ_LIMIT];
244 extern u32 start_pattern, end_pattern;
246 extern u32 maxt_poll_tries;
247 extern u32 is_bist_reset_bit;
248 extern u8 debug_training_bist;
250 extern u8 vref_window_size[MAX_INTERFACE_NUM][MAX_BUS_NUM];
251 extern u32 debug_mode;
252 extern u32 effective_cs;
253 extern int ddr3_tip_centr_skip_min_win_check;
254 extern u32 *dq_map_table;
255 extern enum auto_tune_stage training_stage;
256 extern u8 debug_centralization;
258 extern u32 delay_enable;
259 extern u32 start_pattern, end_pattern;
260 extern u32 freq_val[DDR_FREQ_LIMIT];
261 extern u8 debug_training_hw_alg;
262 extern enum auto_tune_stage training_stage;
264 extern u8 debug_training_ip;
265 extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
266 extern enum auto_tune_stage training_stage;
267 extern u32 effective_cs;
269 extern u8 debug_leveling;
270 extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
271 extern enum auto_tune_stage training_stage;
272 extern u32 rl_version;
273 extern struct cl_val_per_freq cas_latency_table[];
274 extern u32 start_xsb_offset;
275 extern u32 debug_mode;
276 extern u32 odt_config;
277 extern u32 effective_cs;
278 extern u32 phy_reg1_val;
281 extern u32 effective_cs;
282 extern u16 mask_results_dq_reg_map[];
283 extern enum hws_ddr_freq medium_freq;
284 extern u32 freq_val[];
285 extern enum hws_result training_result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM];
286 extern enum auto_tune_stage training_stage;
287 extern u32 debug_mode;
288 extern u32 *dq_map_table;
291 extern struct cl_val_per_freq cas_latency_table[];
292 extern u32 target_freq;
293 extern struct hws_tip_config_func_db config_func_info[HWS_MAX_DEVICE_NUM];
294 extern u32 clamp_tbl[];
295 extern u32 init_freq;
296 /* list of allowed frequency listed in order of enum hws_ddr_freq */
297 extern u32 freq_val[];
298 extern u8 debug_training_static;
299 extern u32 first_active_if;
302 int ddr3_tip_enable_init_sequence(u32 dev_num);
304 int ddr3_tip_init_a38x(u32 dev_num, u32 board_id);
306 int ddr3_hws_hw_training(void);
307 int ddr3_silicon_pre_init(void);
308 int ddr3_silicon_post_init(void);
309 int ddr3_post_run_alg(void);
310 int ddr3_if_ecc_enabled(void);
311 void ddr3_new_tip_ecc_scrub(void);
313 void ddr3_print_version(void);
314 void ddr3_new_tip_dlb_config(void);
315 struct hws_topology_map *ddr3_get_topology_map(void);
317 int ddr3_if_ecc_enabled(void);
318 int ddr3_tip_reg_write(u32 dev_num, u32 reg_addr, u32 data);
319 int ddr3_tip_reg_read(u32 dev_num, u32 reg_addr, u32 *data, u32 reg_mask);
320 int ddr3_silicon_get_ddr_target_freq(u32 *ddr_freq);
321 int ddr3_tip_a38x_get_freq_config(u8 dev_num, enum hws_ddr_freq freq,
322 struct hws_tip_freq_config_info
324 int ddr3_a38x_update_topology_map(u32 dev_num,
325 struct hws_topology_map *topology_map);
326 int ddr3_tip_a38x_get_init_freq(int dev_num, enum hws_ddr_freq *freq);
327 int ddr3_tip_a38x_get_medium_freq(int dev_num, enum hws_ddr_freq *freq);
328 int ddr3_tip_a38x_if_read(u8 dev_num, enum hws_access_type interface_access,
329 u32 if_id, u32 reg_addr, u32 *data, u32 mask);
330 int ddr3_tip_a38x_if_write(u8 dev_num, enum hws_access_type interface_access,
331 u32 if_id, u32 reg_addr, u32 data, u32 mask);
332 int ddr3_tip_a38x_get_device_info(u8 dev_num,
333 struct ddr3_device_info *info_ptr);
335 int ddr3_tip_init_a38x(u32 dev_num, u32 board_id);
337 int print_adll(u32 dev_num, u32 adll[MAX_INTERFACE_NUM * MAX_BUS_NUM]);
338 int ddr3_tip_restore_dunit_regs(u32 dev_num);
339 void print_topology(struct hws_topology_map *topology_db);
341 u32 mv_board_id_get(void);
343 int ddr3_load_topology_map(void);
344 int ddr3_tip_init_specific_reg_config(u32 dev_num,
345 struct reg_data *reg_config_arr);
346 u32 ddr3_tip_get_init_freq(void);
347 void ddr3_hws_set_log_level(enum ddr_lib_debug_block block, u8 level);
348 int ddr3_tip_tune_training_params(u32 dev_num,
349 struct tune_train_params *params);
350 void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
351 int ddr3_fast_path_dynamic_cs_size_config(u32 cs_ena);
352 void ddr3_fast_path_static_cs_size_config(u32 cs_ena);
353 u32 ddr3_get_device_width(u32 cs);
354 u32 mv_board_id_index_get(u32 board_id);
355 u32 mv_board_id_get(void);
356 u32 ddr3_get_bus_width(void);
357 void ddr3_set_log_level(u32 n_log_level);
358 int ddr3_calc_mem_cs_size(u32 cs, u32 *cs_size);
360 int hws_ddr3_cs_base_adr_calc(u32 if_id, u32 cs, u32 *cs_base_addr);
362 int ddr3_tip_print_pbs_result(u32 dev_num, u32 cs_num, enum pbs_dir pbs_mode);
363 int ddr3_tip_clean_pbs_result(u32 dev_num, enum pbs_dir pbs_mode);
365 int ddr3_tip_static_round_trip_arr_build(u32 dev_num,
366 struct trip_delay_element *table_ptr,
367 int is_wl, u32 *round_trip_delay_arr);
369 u32 hws_ddr3_tip_max_cs_get(void);
372 * Accessor functions for the registers
374 static inline void reg_write(u32 addr, u32 val)
376 writel(val, INTER_REGS_BASE + addr);
379 static inline u32 reg_read(u32 addr)
381 return readl(INTER_REGS_BASE + addr);
384 static inline void reg_bit_set(u32 addr, u32 mask)
386 setbits_le32(INTER_REGS_BASE + addr, mask);
389 static inline void reg_bit_clr(u32 addr, u32 mask)
391 clrbits_le32(INTER_REGS_BASE + addr, mask);
394 #endif /* _DDR3_INIT_H */