2 * Copyright (C) Marvell International Ltd. and its affiliates
4 * SPDX-License-Identifier: GPL-2.0
7 #ifndef _DDR3_LOGGING_CONFIG_H
8 #define _DDR3_LOGGING_CONFIG_H
11 #define DEBUG_TRAINING_BIST_ENGINE(level, s)
12 #define DEBUG_TRAINING_IP(level, s)
13 #define DEBUG_CENTRALIZATION_ENGINE(level, s)
14 #define DEBUG_TRAINING_HW_ALG(level, s)
15 #define DEBUG_TRAINING_IP_ENGINE(level, s)
16 #define DEBUG_LEVELING(level, s)
17 #define DEBUG_PBS_ENGINE(level, s)
18 #define DEBUG_TRAINING_STATIC_IP(level, s)
19 #define DEBUG_TRAINING_ACCESS(level, s)
21 #ifdef LIB_FUNCTIONAL_DEBUG_ONLY
22 #define DEBUG_TRAINING_BIST_ENGINE(level, s)
23 #define DEBUG_TRAINING_IP_ENGINE(level, s)
24 #define DEBUG_TRAINING_IP(level, s) \
25 if (level >= debug_training) \
27 #define DEBUG_CENTRALIZATION_ENGINE(level, s) \
28 if (level >= debug_centralization) \
30 #define DEBUG_TRAINING_HW_ALG(level, s) \
31 if (level >= debug_training_hw_alg) \
33 #define DEBUG_LEVELING(level, s) \
34 if (level >= debug_leveling) \
36 #define DEBUG_PBS_ENGINE(level, s) \
37 if (level >= debug_pbs) \
39 #define DEBUG_TRAINING_STATIC_IP(level, s) \
40 if (level >= debug_training_static) \
42 #define DEBUG_TRAINING_ACCESS(level, s) \
43 if (level >= debug_training_access) \
46 #define DEBUG_TRAINING_BIST_ENGINE(level, s) \
47 if (level >= debug_training_bist) \
50 #define DEBUG_TRAINING_IP_ENGINE(level, s) \
51 if (level >= debug_training_ip) \
53 #define DEBUG_TRAINING_IP(level, s) \
54 if (level >= debug_training) \
56 #define DEBUG_CENTRALIZATION_ENGINE(level, s) \
57 if (level >= debug_centralization) \
59 #define DEBUG_TRAINING_HW_ALG(level, s) \
60 if (level >= debug_training_hw_alg) \
62 #define DEBUG_LEVELING(level, s) \
63 if (level >= debug_leveling) \
65 #define DEBUG_PBS_ENGINE(level, s) \
66 if (level >= debug_pbs) \
68 #define DEBUG_TRAINING_STATIC_IP(level, s) \
69 if (level >= debug_training_static) \
71 #define DEBUG_TRAINING_ACCESS(level, s) \
72 if (level >= debug_training_access) \
78 #define DEBUG_LEVEL_TRACE 1
79 #define DEBUG_LEVEL_INFO 2
80 #define DEBUG_LEVEL_ERROR 3
82 enum ddr_lib_debug_block {
84 DEBUG_BLOCK_TRAINING_MAIN,
86 DEBUG_BLOCK_CENTRALIZATION,
93 DEBUG_STAGES_REG_DUMP,
94 /* All excluding IP and REG_DUMP, should be enabled separatelly */
98 int ddr3_tip_print_log(u32 dev_num, u32 mem_addr);
99 int ddr3_tip_print_stability_log(u32 dev_num);
101 #endif /* _DDR3_LOGGING_CONFIG_H */