2 * Copyright (C) Marvell International Ltd. and its affiliates
4 * SPDX-License-Identifier: GPL-2.0
7 #ifndef _DDR3_TRAINING_IP_H_
8 #define _DDR3_TRAINING_IP_H_
10 #include "ddr3_training_ip_def.h"
11 #include "ddr_topology_def.h"
12 #include "ddr_training_ip_db.h"
14 #define DDR3_TIP_VERSION_STRING "DDR3 Training Sequence - Ver TIP-1.29."
17 #define MAX_TOTAL_BUS_NUM (MAX_INTERFACE_NUM * MAX_BUS_NUM)
20 #define GET_MIN(arg1, arg2) ((arg1) < (arg2)) ? (arg1) : (arg2)
21 #define GET_MAX(arg1, arg2) ((arg1) < (arg2)) ? (arg2) : (arg1)
23 #define INIT_CONTROLLER_MASK_BIT 0x00000001
24 #define STATIC_LEVELING_MASK_BIT 0x00000002
25 #define SET_LOW_FREQ_MASK_BIT 0x00000004
26 #define LOAD_PATTERN_MASK_BIT 0x00000008
27 #define SET_MEDIUM_FREQ_MASK_BIT 0x00000010
28 #define WRITE_LEVELING_MASK_BIT 0x00000020
29 #define LOAD_PATTERN_2_MASK_BIT 0x00000040
30 #define READ_LEVELING_MASK_BIT 0x00000080
31 #define SW_READ_LEVELING_MASK_BIT 0x00000100
32 #define WRITE_LEVELING_SUPP_MASK_BIT 0x00000200
33 #define PBS_RX_MASK_BIT 0x00000400
34 #define PBS_TX_MASK_BIT 0x00000800
35 #define SET_TARGET_FREQ_MASK_BIT 0x00001000
36 #define ADJUST_DQS_MASK_BIT 0x00002000
37 #define WRITE_LEVELING_TF_MASK_BIT 0x00004000
38 #define LOAD_PATTERN_HIGH_MASK_BIT 0x00008000
39 #define READ_LEVELING_TF_MASK_BIT 0x00010000
40 #define WRITE_LEVELING_SUPP_TF_MASK_BIT 0x00020000
41 #define DM_PBS_TX_MASK_BIT 0x00040000
42 #define CENTRALIZATION_RX_MASK_BIT 0x00100000
43 #define CENTRALIZATION_TX_MASK_BIT 0x00200000
44 #define TX_EMPHASIS_MASK_BIT 0x00400000
45 #define PER_BIT_READ_LEVELING_TF_MASK_BIT 0x00800000
46 #define VREF_CALIBRATION_MASK_BIT 0x01000000
54 enum hws_training_result {
59 enum auto_tune_stage {
75 WRITE_LEVELING_SUPP_TF,
82 PER_BIT_READ_LEVELING_TF,
86 enum hws_access_type {
87 ACCESS_TYPE_UNICAST = 0,
88 ACCESS_TYPE_MULTICAST = 1
96 struct init_cntr_param {
103 struct pattern_info {
106 u8 delay_between_bursts;
112 /* CL value for each frequency */
113 struct cl_val_per_freq {
114 u8 cl_val[DDR_FREQ_LIMIT];
123 /* 32 bits representing MRS bits */
124 u32 reg_mr0[MAX_INTERFACE_NUM];
125 u32 reg_mr1[MAX_INTERFACE_NUM];
126 u32 reg_mr2[MAX_INTERFACE_NUM];
127 u32 reg_m_r3[MAX_INTERFACE_NUM];
129 * Each element in array represent read_data_sample register delay for
130 * a specific interface.
131 * Each register, 4 bits[0+CS*8 to 4+CS*8] represent Number of DDR
132 * cycles from read command until data is ready to be fetched from
133 * the PHY, when accessing CS.
135 u32 read_data_sample[MAX_INTERFACE_NUM];
137 * Each element in array represent read_data_sample register delay for
138 * a specific interface.
139 * Each register, 4 bits[0+CS*8 to 4+CS*8] represent the total delay
140 * from read command until opening the read mask, when accessing CS.
141 * This field defines the delay in DDR cycles granularity.
143 u32 read_data_ready[MAX_INTERFACE_NUM];
146 struct hws_tip_freq_config_info {
152 struct hws_cs_config_info {
162 struct hws_xsb_info {
163 struct dfx_access *dfx_table;
166 int ddr3_tip_register_dq_table(u32 dev_num, u32 *table);
167 int hws_ddr3_tip_select_ddr_controller(u32 dev_num, int enable);
168 int hws_ddr3_tip_init_controller(u32 dev_num,
169 struct init_cntr_param *init_cntr_prm);
170 int hws_ddr3_tip_load_topology_map(u32 dev_num,
171 struct hws_topology_map *topology);
172 int hws_ddr3_tip_run_alg(u32 dev_num, enum hws_algo_type algo_type);
173 int hws_ddr3_tip_mode_read(u32 dev_num, struct mode_info *mode_info);
174 int hws_ddr3_tip_read_training_result(u32 dev_num,
175 enum hws_result result[MAX_STAGE_LIMIT][MAX_INTERFACE_NUM]);
176 int ddr3_tip_is_pup_lock(u32 *pup_buf, enum hws_training_result read_mode);
177 u8 ddr3_tip_get_buf_min(u8 *buf_ptr);
178 u8 ddr3_tip_get_buf_max(u8 *buf_ptr);
180 #endif /* _DDR3_TRAINING_IP_H_ */