2 * Copyright (C) Marvell International Ltd. and its affiliates
4 * SPDX-License-Identifier: GPL-2.0
7 #ifndef _DDR3_TRAINING_IP_BIST_H_
8 #define _DDR3_TRAINING_IP_BIST_H_
10 #include "ddr3_training_ip.h"
12 enum hws_bist_operation {
17 enum hws_stress_jump {
22 enum hws_pattern_duration {
24 DURATION_STOP_AT_FAIL = 1,
33 u32 bist_last_fail_addr;
36 int ddr3_tip_bist_read_result(u32 dev_num, u32 if_id,
37 struct bist_result *pst_bist_result);
38 int ddr3_tip_bist_activate(u32 dev_num, enum hws_pattern pattern,
39 enum hws_access_type access_type,
40 u32 if_num, enum hws_dir direction,
41 enum hws_stress_jump addr_stress_jump,
42 enum hws_pattern_duration duration,
43 enum hws_bist_operation oper_type,
44 u32 offset, u32 cs_num, u32 pattern_addr_length);
45 int hws_ddr3_run_bist(u32 dev_num, enum hws_pattern pattern, u32 *result,
47 int ddr3_tip_run_sweep_test(int dev_num, u32 repeat_num, u32 direction,
49 int ddr3_tip_print_regs(u32 dev_num);
50 int ddr3_tip_reg_dump(u32 dev_num);
51 int run_xsb_test(u32 dev_num, u32 mem_addr, u32 write_type, u32 read_type,
54 #endif /* _DDR3_TRAINING_IP_BIST_H_ */