git.sur5r.net Git - u-boot/blob - drivers/ddr/marvell/a38x/ddr3_training_ip_bist.h

   1 /*
   2  * Copyright (C) Marvell International Ltd. and its affiliates
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0
   5  */
   6
   7 #ifndef _DDR3_TRAINING_IP_BIST_H_
   8 #define _DDR3_TRAINING_IP_BIST_H_
   9
  10 #include "ddr3_training_ip.h"
  11
  12 enum hws_bist_operation {
  13         BIST_STOP = 0,
  14         BIST_START = 1
  15 };
  16
  17 enum  hws_stress_jump {
  18         STRESS_NONE = 0,
  19         STRESS_ENABLE = 1
  20 };
  21
  22 enum hws_pattern_duration {
  23         DURATION_SINGLE = 0,
  24         DURATION_STOP_AT_FAIL = 1,
  25         DURATION_ADDRESS = 2,
  26         DURATION_CONT = 4
  27 };
  28
  29 struct bist_result {
  30         u32 bist_error_cnt;
  31         u32 bist_fail_low;
  32         u32 bist_fail_high;
  33         u32 bist_last_fail_addr;
  34 };
  35
  36 int ddr3_tip_bist_read_result(u32 dev_num, u32 if_id,
  37                               struct bist_result *pst_bist_result);
  38 int ddr3_tip_bist_activate(u32 dev_num, enum hws_pattern pattern,
  39                            enum hws_access_type access_type,
  40                            u32 if_num, enum hws_dir direction,
  41                            enum hws_stress_jump addr_stress_jump,
  42                            enum hws_pattern_duration duration,
  43                            enum hws_bist_operation oper_type,
  44                            u32 offset, u32 cs_num, u32 pattern_addr_length);
  45 int hws_ddr3_run_bist(u32 dev_num, enum hws_pattern pattern, u32 *result,
  46                       u32 cs_num);
  47 int ddr3_tip_run_sweep_test(int dev_num, u32 repeat_num, u32 direction,
  48                             u32 mode);
  49 int ddr3_tip_print_regs(u32 dev_num);
  50 int ddr3_tip_reg_dump(u32 dev_num);
  51 int run_xsb_test(u32 dev_num, u32 mem_addr, u32 write_type, u32 read_type,
  52                  u32 burst_length);
  53
  54 #endif /* _DDR3_TRAINING_IP_BIST_H_ */