1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) Marvell International Ltd. and its affiliates
9 #include <asm/arch/cpu.h>
10 #include <asm/arch/soc.h>
12 #include "ddr3_init.h"
14 /* Design Guidelines parameters */
15 u32 g_zpri_data = 123; /* controller data - P drive strength */
16 u32 g_znri_data = 123; /* controller data - N drive strength */
17 u32 g_zpri_ctrl = 74; /* controller C/A - P drive strength */
18 u32 g_znri_ctrl = 74; /* controller C/A - N drive strength */
19 u32 g_zpodt_data = 45; /* controller data - P ODT */
20 u32 g_znodt_data = 45; /* controller data - N ODT */
21 u32 g_zpodt_ctrl = 45; /* controller data - P ODT */
22 u32 g_znodt_ctrl = 45; /* controller data - N ODT */
23 u32 g_odt_config_2cs = 0x120012;
24 u32 g_odt_config_1cs = 0x10000;
30 * Configure phy (called by static init controller) for static flow
32 int ddr3_tip_configure_phy(u32 dev_num)
35 struct hws_topology_map *tm = ddr3_get_topology_map();
37 CHECK_STATUS(ddr3_tip_bus_write
38 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
39 ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA,
40 PAD_ZRI_CALIB_PHY_REG,
41 ((0x7f & g_zpri_data) << 7 | (0x7f & g_znri_data))));
42 CHECK_STATUS(ddr3_tip_bus_write
43 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
44 ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_CONTROL,
45 PAD_ZRI_CALIB_PHY_REG,
46 ((0x7f & g_zpri_ctrl) << 7 | (0x7f & g_znri_ctrl))));
47 CHECK_STATUS(ddr3_tip_bus_write
48 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
49 ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA,
50 PAD_ODT_CALIB_PHY_REG,
51 ((0x3f & g_zpodt_data) << 6 | (0x3f & g_znodt_data))));
52 CHECK_STATUS(ddr3_tip_bus_write
53 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
54 ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_CONTROL,
55 PAD_ODT_CALIB_PHY_REG,
56 ((0x3f & g_zpodt_ctrl) << 6 | (0x3f & g_znodt_ctrl))));
58 CHECK_STATUS(ddr3_tip_bus_write
59 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
60 ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA,
61 PAD_PRE_DISABLE_PHY_REG, 0));
62 CHECK_STATUS(ddr3_tip_bus_write
63 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
64 ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA,
65 CMOS_CONFIG_PHY_REG, 0));
66 CHECK_STATUS(ddr3_tip_bus_write
67 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
68 ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_CONTROL,
69 CMOS_CONFIG_PHY_REG, 0));
71 for (if_id = 0; if_id <= MAX_INTERFACE_NUM - 1; if_id++) {
72 /* check if the interface is enabled */
73 VALIDATE_ACTIVE(tm->if_act_mask, if_id);
76 phy_id < tm->num_of_bus_per_interface;
78 VALIDATE_ACTIVE(tm->bus_act_mask, phy_id);
80 CHECK_STATUS(ddr3_tip_bus_read_modify_write
81 (dev_num, ACCESS_TYPE_UNICAST,
82 if_id, phy_id, DDR_PHY_DATA,
84 ((clamp_tbl[if_id] << 4) | vref),
86 /* clamp not relevant for control */
87 CHECK_STATUS(ddr3_tip_bus_read_modify_write
88 (dev_num, ACCESS_TYPE_UNICAST,
89 if_id, phy_id, DDR_PHY_CONTROL,
90 PAD_CONFIG_PHY_REG, 0x4, 0x7));
94 CHECK_STATUS(ddr3_tip_bus_write
95 (dev_num, ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE,
96 ACCESS_TYPE_MULTICAST, PARAM_NOT_CARE, DDR_PHY_DATA, 0x90,