1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) Marvell International Ltd. and its affiliates
6 #include "mv_ddr_topology.h"
7 #include "mv_ddr_common.h"
8 #include "mv_ddr_spd.h"
10 #include "ddr_topology_def.h"
11 #include "ddr3_training_ip_db.h"
12 #include "ddr3_training_ip.h"
15 unsigned int mv_ddr_cl_calc(unsigned int taa_min, unsigned int tclk)
17 unsigned int cl = ceil_div(taa_min, tclk);
19 return mv_ddr_spd_supported_cl_get(cl);
23 unsigned int mv_ddr_cwl_calc(unsigned int tclk)
29 else if (tclk >= 1071)
41 struct mv_ddr_topology_map *mv_ddr_topology_map_update(void)
43 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
44 unsigned int octets_per_if_num = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
45 enum hws_speed_bin speed_bin_index;
46 enum hws_ddr_freq freq = DDR_FREQ_LAST;
48 unsigned char val = 0;
52 if (tm->interface_params[0].memory_freq == DDR_FREQ_SAR)
53 tm->interface_params[0].memory_freq = mv_ddr_init_freq_get();
55 if (tm->cfg_src == MV_DDR_CFG_SPD) {
56 /* check dram device type */
57 val = mv_ddr_spd_dev_type_get(&tm->spd_data);
58 if (val != MV_DDR_SPD_DEV_TYPE_DDR4) {
59 printf("mv_ddr: unsupported dram device type found\n");
63 /* update topology map with timing data */
64 if (mv_ddr_spd_timing_calc(&tm->spd_data, tm->timing_data) > 0) {
65 printf("mv_ddr: negative timing data found\n");
69 /* update device width in topology map */
70 tm->interface_params[0].bus_width = mv_ddr_spd_dev_width_get(&tm->spd_data);
72 /* update die capacity in topology map */
73 tm->interface_params[0].memory_size = mv_ddr_spd_die_capacity_get(&tm->spd_data);
75 /* update bus bit mask in topology map */
76 tm->bus_act_mask = mv_ddr_bus_bit_mask_get();
78 /* update cs bit mask in topology map */
79 val = mv_ddr_spd_cs_bit_mask_get(&tm->spd_data);
80 for (i = 0; i < octets_per_if_num; i++) {
81 tm->interface_params[0].as_bus_params[i].cs_bitmask = val;
84 /* check dram module type */
85 val = mv_ddr_spd_module_type_get(&tm->spd_data);
87 case MV_DDR_SPD_MODULE_TYPE_UDIMM:
88 case MV_DDR_SPD_MODULE_TYPE_SO_DIMM:
89 case MV_DDR_SPD_MODULE_TYPE_MINI_UDIMM:
90 case MV_DDR_SPD_MODULE_TYPE_72BIT_SO_UDIMM:
91 case MV_DDR_SPD_MODULE_TYPE_16BIT_SO_DIMM:
92 case MV_DDR_SPD_MODULE_TYPE_32BIT_SO_DIMM:
95 printf("mv_ddr: unsupported dram module type found\n");
99 /* update mirror bit mask in topology map */
100 val = mv_ddr_spd_mem_mirror_get(&tm->spd_data);
101 for (i = 0; i < octets_per_if_num; i++) {
102 tm->interface_params[0].as_bus_params[i].mirror_enable_bitmask = val << 1;
105 tclk = 1000000 / freq_val[tm->interface_params[0].memory_freq];
106 /* update cas write latency (cwl) */
107 val = mv_ddr_cwl_calc(tclk);
109 printf("mv_ddr: unsupported cas write latency value found\n");
112 tm->interface_params[0].cas_wl = val;
114 /* update cas latency (cl) */
115 mv_ddr_spd_supported_cls_calc(&tm->spd_data);
116 val = mv_ddr_cl_calc(tm->timing_data[MV_DDR_TAA_MIN], tclk);
118 printf("mv_ddr: unsupported cas latency value found\n");
121 tm->interface_params[0].cas_l = val;
122 } else if (tm->cfg_src == MV_DDR_CFG_DEFAULT) {
123 /* set cas and cas-write latencies per speed bin, if they unset */
124 speed_bin_index = tm->interface_params[0].speed_bin_index;
125 freq = tm->interface_params[0].memory_freq;
127 if (tm->interface_params[0].cas_l == 0)
128 tm->interface_params[0].cas_l =
129 cas_latency_table[speed_bin_index].cl_val[freq];
131 if (tm->interface_params[0].cas_wl == 0)
132 tm->interface_params[0].cas_wl =
133 cas_write_latency_table[speed_bin_index].cl_val[freq];
140 unsigned short mv_ddr_bus_bit_mask_get(void)
142 unsigned short pri_and_ext_bus_width = 0x0;
143 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
144 unsigned int octets_per_if_num = ddr3_tip_dev_attr_get(0, MV_ATTR_OCTET_PER_INTERFACE);
146 if (tm->cfg_src == MV_DDR_CFG_SPD) {
147 enum mv_ddr_pri_bus_width pri_bus_width = mv_ddr_spd_pri_bus_width_get(&tm->spd_data);
148 enum mv_ddr_bus_width_ext bus_width_ext = mv_ddr_spd_bus_width_ext_get(&tm->spd_data);
150 switch (pri_bus_width) {
151 case MV_DDR_PRI_BUS_WIDTH_16:
152 pri_and_ext_bus_width = BUS_MASK_16BIT;
154 case MV_DDR_PRI_BUS_WIDTH_32:
155 pri_and_ext_bus_width = BUS_MASK_32BIT;
157 case MV_DDR_PRI_BUS_WIDTH_64:
158 pri_and_ext_bus_width = MV_DDR_64BIT_BUS_MASK;
161 pri_and_ext_bus_width = 0x0;
164 if (bus_width_ext == MV_DDR_BUS_WIDTH_EXT_8)
165 pri_and_ext_bus_width |= 1 << (octets_per_if_num - 1);
168 return pri_and_ext_bus_width;
171 unsigned int mv_ddr_if_bus_width_get(void)
173 struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get();
174 unsigned int bus_width;
176 switch (tm->bus_act_mask) {
178 case BUS_MASK_16BIT_ECC:
179 case BUS_MASK_16BIT_ECC_PUP3:
183 case BUS_MASK_32BIT_ECC:
184 case MV_DDR_32BIT_ECC_PUP8_BUS_MASK:
187 case MV_DDR_64BIT_BUS_MASK:
188 case MV_DDR_64BIT_ECC_PUP8_BUS_MASK:
192 printf("mv_ddr: unsupported bus active mask parameter found\n");