1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (C) Marvell International Ltd. and its affiliates
6 #ifndef _MV_DDR_TOPOLOGY_H
7 #define _MV_DDR_TOPOLOGY_H
10 #define BUS_MASK_32BIT 0xf
11 #define BUS_MASK_32BIT_ECC 0x1f
12 #define BUS_MASK_16BIT 0x3
13 #define BUS_MASK_16BIT_ECC 0x13
14 #define BUS_MASK_16BIT_ECC_PUP3 0xb
15 #define MV_DDR_64BIT_BUS_MASK 0xff
16 #define MV_DDR_64BIT_ECC_PUP8_BUS_MASK 0x1ff
17 #define MV_DDR_32BIT_ECC_PUP8_BUS_MASK 0x10f
19 /* source of ddr configuration data */
21 MV_DDR_CFG_DEFAULT, /* based on data in mv_ddr_topology_map structure */
22 MV_DDR_CFG_SPD, /* based on data in spd */
23 MV_DDR_CFG_USER, /* based on data from user */
24 MV_DDR_CFG_STATIC, /* based on data from user in register-value format */
28 enum mv_ddr_num_of_sub_phys_per_ddr_unit {
33 enum mv_ddr_temperature {
45 enum mv_ddr_timing_data {
46 MV_DDR_TCK_AVG_MIN, /* sdram min cycle time (t ck avg min) */
47 MV_DDR_TAA_MIN, /* min cas latency time (t aa min) */
48 MV_DDR_TRFC1_MIN, /* min refresh recovery delay time (t rfc1 min) */
49 MV_DDR_TWR_MIN, /* min write recovery time (t wr min) */
50 MV_DDR_TRCD_MIN, /* min ras to cas delay time (t rcd min) */
51 MV_DDR_TRP_MIN, /* min row precharge delay time (t rp min) */
52 MV_DDR_TRC_MIN, /* min active to active/refresh delay time (t rc min) */
53 MV_DDR_TRAS_MIN, /* min active to precharge delay time (t ras min) */
54 MV_DDR_TRRD_S_MIN, /* min activate to activate delay time (t rrd_s min), diff bank group */
55 MV_DDR_TRRD_L_MIN, /* min activate to activate delay time (t rrd_l min), same bank group */
56 MV_DDR_TFAW_MIN, /* min four activate window delay time (t faw min) */
57 MV_DDR_TWTR_S_MIN, /* min write to read time (t wtr s min), diff bank group */
58 MV_DDR_TWTR_L_MIN, /* min write to read time (t wtr l min), same bank group */
62 enum mv_ddr_dev_width { /* sdram device width */
63 MV_DDR_DEV_WIDTH_4BIT,
64 MV_DDR_DEV_WIDTH_8BIT,
65 MV_DDR_DEV_WIDTH_16BIT,
66 MV_DDR_DEV_WIDTH_32BIT,
70 enum mv_ddr_die_capacity { /* total sdram capacity per die, megabits */
71 MV_DDR_DIE_CAP_256MBIT,
72 MV_DDR_DIE_CAP_512MBIT = 0,
77 MV_DDR_DIE_CAP_16GBIT,
78 MV_DDR_DIE_CAP_32GBIT,
79 MV_DDR_DIE_CAP_12GBIT,
80 MV_DDR_DIE_CAP_24GBIT,
84 enum mv_ddr_pkg_rank { /* number of package ranks per dimm */
96 enum mv_ddr_pri_bus_width { /* number of primary bus width bits */
97 MV_DDR_PRI_BUS_WIDTH_8,
98 MV_DDR_PRI_BUS_WIDTH_16,
99 MV_DDR_PRI_BUS_WIDTH_32,
100 MV_DDR_PRI_BUS_WIDTH_64,
101 MV_DDR_PRI_BUS_WIDTH_LAST
104 enum mv_ddr_bus_width_ext { /* number of extension bus width bits */
105 MV_DDR_BUS_WIDTH_EXT_0,
106 MV_DDR_BUS_WIDTH_EXT_8,
107 MV_DDR_BUS_WIDTH_EXT_LAST
110 enum mv_ddr_die_count {
122 unsigned int mv_ddr_cl_calc(unsigned int taa_min, unsigned int tclk);
123 unsigned int mv_ddr_cwl_calc(unsigned int tclk);
124 struct mv_ddr_topology_map *mv_ddr_topology_map_update(void);
125 struct dram_config *mv_ddr_dram_config_update(void);
126 unsigned short mv_ddr_bus_bit_mask_get(void);
127 unsigned int mv_ddr_if_bus_width_get(void);
129 #endif /* _MV_DDR_TOPOLOGY_H */