2 * Freescale i.MX28 APBH DMA driver
4 * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
5 * on behalf of DENX Software Engineering GmbH
7 * Based on code from LTIB:
8 * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License along
21 * with this program; if not, write to the Free Software Foundation, Inc.,
22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
25 #include <linux/list.h>
29 #include <asm/errno.h>
31 #include <asm/arch/clock.h>
32 #include <asm/arch/imx-regs.h>
33 #include <asm/arch/sys_proto.h>
34 #include <asm/arch/dma.h>
36 static struct mxs_dma_chan mxs_dma_channels[MXS_MAX_DMA_CHANNELS];
39 * Test is the DMA channel is valid channel
41 int mxs_dma_validate_chan(int channel)
43 struct mxs_dma_chan *pchan;
45 if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS))
48 pchan = mxs_dma_channels + channel;
49 if (!(pchan->flags & MXS_DMA_FLAGS_ALLOCATED))
56 * Enable a DMA channel.
58 * If the given channel has any DMA descriptors on its active list, this
59 * function causes the DMA hardware to begin processing them.
61 * This function marks the DMA channel as "busy," whether or not there are any
62 * descriptors to process.
64 int mxs_dma_enable(int channel)
66 struct mx28_apbh_regs *apbh_regs =
67 (struct mx28_apbh_regs *)MXS_APBH_BASE;
69 struct mxs_dma_chan *pchan;
70 struct mxs_dma_desc *pdesc;
73 ret = mxs_dma_validate_chan(channel);
77 pchan = mxs_dma_channels + channel;
79 if (pchan->pending_num == 0) {
80 pchan->flags |= MXS_DMA_FLAGS_BUSY;
84 pdesc = list_first_entry(&pchan->active, struct mxs_dma_desc, node);
88 if (pchan->flags & MXS_DMA_FLAGS_BUSY) {
89 if (!(pdesc->cmd.data & MXS_DMA_DESC_CHAIN))
92 sem = mxs_dma_read_semaphore(channel);
97 pdesc = list_entry(pdesc->node.next,
98 struct mxs_dma_desc, node);
99 writel(mxs_dma_cmd_address(pdesc),
100 &apbh_regs->ch[channel].hw_apbh_ch_nxtcmdar);
102 writel(pchan->pending_num,
103 &apbh_regs->ch[channel].hw_apbh_ch_sema);
104 pchan->active_num += pchan->pending_num;
105 pchan->pending_num = 0;
107 pchan->active_num += pchan->pending_num;
108 pchan->pending_num = 0;
109 writel(mxs_dma_cmd_address(pdesc),
110 &apbh_regs->ch[channel].hw_apbh_ch_nxtcmdar);
111 writel(pchan->active_num,
112 &apbh_regs->ch[channel].hw_apbh_ch_sema);
113 writel(1 << (channel + APBH_CTRL0_CLKGATE_CHANNEL_OFFSET),
114 &apbh_regs->hw_apbh_ctrl0_clr);
117 pchan->flags |= MXS_DMA_FLAGS_BUSY;
122 * Disable a DMA channel.
124 * This function shuts down a DMA channel and marks it as "not busy." Any
125 * descriptors on the active list are immediately moved to the head of the
126 * "done" list, whether or not they have actually been processed by the
127 * hardware. The "ready" flags of these descriptors are NOT cleared, so they
128 * still appear to be active.
130 * This function immediately shuts down a DMA channel's hardware, aborting any
131 * I/O that may be in progress, potentially leaving I/O hardware in an undefined
132 * state. It is unwise to call this function if there is ANY chance the hardware
133 * is still processing a command.
135 int mxs_dma_disable(int channel)
137 struct mxs_dma_chan *pchan;
138 struct mx28_apbh_regs *apbh_regs =
139 (struct mx28_apbh_regs *)MXS_APBH_BASE;
142 ret = mxs_dma_validate_chan(channel);
146 pchan = mxs_dma_channels + channel;
148 if (!(pchan->flags & MXS_DMA_FLAGS_BUSY))
151 writel(1 << (channel + APBH_CTRL0_CLKGATE_CHANNEL_OFFSET),
152 &apbh_regs->hw_apbh_ctrl0_set);
154 pchan->flags &= ~MXS_DMA_FLAGS_BUSY;
155 pchan->active_num = 0;
156 pchan->pending_num = 0;
157 list_splice_init(&pchan->active, &pchan->done);
163 * Resets the DMA channel hardware.
165 int mxs_dma_reset(int channel)
167 struct mx28_apbh_regs *apbh_regs =
168 (struct mx28_apbh_regs *)MXS_APBH_BASE;
171 ret = mxs_dma_validate_chan(channel);
175 writel(1 << (channel + APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET),
176 &apbh_regs->hw_apbh_channel_ctrl_set);
182 * Freeze a DMA channel.
184 * This function causes the channel to continuously fail arbitration for bus
185 * access, which halts all forward progress without losing any state. A call to
186 * mxs_dma_unfreeze() will cause the channel to continue its current operation
187 * with no ill effect.
189 int mxs_dma_freeze(int channel)
191 struct mx28_apbh_regs *apbh_regs =
192 (struct mx28_apbh_regs *)MXS_APBH_BASE;
195 ret = mxs_dma_validate_chan(channel);
199 writel(1 << (channel + APBH_CHANNEL_CTRL_FREEZE_CHANNEL_OFFSET),
200 &apbh_regs->hw_apbh_channel_ctrl_set);
206 * Unfreeze a DMA channel.
208 * This function reverses the effect of mxs_dma_freeze(), enabling the DMA
209 * channel to continue from where it was frozen.
211 int mxs_dma_unfreeze(int channel)
213 struct mx28_apbh_regs *apbh_regs =
214 (struct mx28_apbh_regs *)MXS_APBH_BASE;
217 ret = mxs_dma_validate_chan(channel);
221 writel(1 << (channel + APBH_CHANNEL_CTRL_FREEZE_CHANNEL_OFFSET),
222 &apbh_regs->hw_apbh_channel_ctrl_clr);
228 * Read a DMA channel's hardware semaphore.
230 * As used by the MXS platform's DMA software, the DMA channel's hardware
231 * semaphore reflects the number of DMA commands the hardware will process, but
232 * has not yet finished. This is a volatile value read directly from hardware,
233 * so it must be be viewed as immediately stale.
235 * If the channel is not marked busy, or has finished processing all its
236 * commands, this value should be zero.
238 * See mxs_dma_append() for details on how DMA command blocks must be configured
239 * to maintain the expected behavior of the semaphore's value.
241 int mxs_dma_read_semaphore(int channel)
243 struct mx28_apbh_regs *apbh_regs =
244 (struct mx28_apbh_regs *)MXS_APBH_BASE;
248 ret = mxs_dma_validate_chan(channel);
252 tmp = readl(&apbh_regs->ch[channel].hw_apbh_ch_sema);
254 tmp &= APBH_CHn_SEMA_PHORE_MASK;
255 tmp >>= APBH_CHn_SEMA_PHORE_OFFSET;
261 * Enable or disable DMA interrupt.
263 * This function enables the given DMA channel to interrupt the CPU.
265 int mxs_dma_enable_irq(int channel, int enable)
267 struct mx28_apbh_regs *apbh_regs =
268 (struct mx28_apbh_regs *)MXS_APBH_BASE;
271 ret = mxs_dma_validate_chan(channel);
276 writel(1 << (channel + APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET),
277 &apbh_regs->hw_apbh_ctrl1_set);
279 writel(1 << (channel + APBH_CTRL1_CH_CMDCMPLT_IRQ_EN_OFFSET),
280 &apbh_regs->hw_apbh_ctrl1_clr);
286 * Check if a DMA interrupt is pending.
288 int mxs_dma_irq_is_pending(int channel)
290 struct mx28_apbh_regs *apbh_regs =
291 (struct mx28_apbh_regs *)MXS_APBH_BASE;
295 ret = mxs_dma_validate_chan(channel);
299 tmp = readl(&apbh_regs->hw_apbh_ctrl1);
300 tmp |= readl(&apbh_regs->hw_apbh_ctrl2);
302 return (tmp >> channel) & 1;
306 * Clear DMA interrupt.
308 * The software that is using the DMA channel must register to receive its
309 * interrupts and, when they arrive, must call this function to clear them.
311 int mxs_dma_ack_irq(int channel)
313 struct mx28_apbh_regs *apbh_regs =
314 (struct mx28_apbh_regs *)MXS_APBH_BASE;
317 ret = mxs_dma_validate_chan(channel);
321 writel(1 << channel, &apbh_regs->hw_apbh_ctrl1_clr);
322 writel(1 << channel, &apbh_regs->hw_apbh_ctrl2_clr);
328 * Request to reserve a DMA channel
330 int mxs_dma_request(int channel)
332 struct mxs_dma_chan *pchan;
334 if ((channel < 0) || (channel >= MXS_MAX_DMA_CHANNELS))
337 pchan = mxs_dma_channels + channel;
338 if ((pchan->flags & MXS_DMA_FLAGS_VALID) != MXS_DMA_FLAGS_VALID)
341 if (pchan->flags & MXS_DMA_FLAGS_ALLOCATED)
344 pchan->flags |= MXS_DMA_FLAGS_ALLOCATED;
345 pchan->active_num = 0;
346 pchan->pending_num = 0;
348 INIT_LIST_HEAD(&pchan->active);
349 INIT_LIST_HEAD(&pchan->done);
355 * Release a DMA channel.
357 * This function releases a DMA channel from its current owner.
359 * The channel will NOT be released if it's marked "busy" (see
362 int mxs_dma_release(int channel)
364 struct mxs_dma_chan *pchan;
367 ret = mxs_dma_validate_chan(channel);
371 pchan = mxs_dma_channels + channel;
373 if (pchan->flags & MXS_DMA_FLAGS_BUSY)
377 pchan->active_num = 0;
378 pchan->pending_num = 0;
379 pchan->flags &= ~MXS_DMA_FLAGS_ALLOCATED;
385 * Allocate DMA descriptor
387 struct mxs_dma_desc *mxs_dma_desc_alloc(void)
389 struct mxs_dma_desc *pdesc;
391 pdesc = memalign(MXS_DMA_ALIGNMENT, sizeof(struct mxs_dma_desc));
396 memset(pdesc, 0, sizeof(*pdesc));
397 pdesc->address = (dma_addr_t)pdesc;
403 * Free DMA descriptor
405 void mxs_dma_desc_free(struct mxs_dma_desc *pdesc)
414 * Return the address of the command within a descriptor.
416 unsigned int mxs_dma_cmd_address(struct mxs_dma_desc *desc)
418 return desc->address + offsetof(struct mxs_dma_desc, cmd);
422 * Check if descriptor is on a channel's active list.
424 * This function returns the state of a descriptor's "ready" flag. This flag is
425 * usually set only if the descriptor appears on a channel's active list. The
426 * descriptor may or may not have already been processed by the hardware.
428 * The "ready" flag is set when the descriptor is submitted to a channel by a
429 * call to mxs_dma_append() or mxs_dma_append_list(). The "ready" flag is
430 * cleared when a processed descriptor is moved off the active list by a call
431 * to mxs_dma_finish(). The "ready" flag is NOT cleared if the descriptor is
432 * aborted by a call to mxs_dma_disable().
434 int mxs_dma_desc_pending(struct mxs_dma_desc *pdesc)
436 return pdesc->flags & MXS_DMA_DESC_READY;
440 * Add a DMA descriptor to a channel.
442 * If the descriptor list for this channel is not empty, this function sets the
443 * CHAIN bit and the NEXTCMD_ADDR fields in the last descriptor's DMA command so
444 * it will chain to the new descriptor's command.
446 * Then, this function marks the new descriptor as "ready," adds it to the end
447 * of the active descriptor list, and increments the count of pending
450 * The MXS platform DMA software imposes some rules on DMA commands to maintain
451 * important invariants. These rules are NOT checked, but they must be carefully
452 * applied by software that uses MXS DMA channels.
455 * The DMA channel's hardware semaphore must reflect the number of DMA
456 * commands the hardware will process, but has not yet finished.
459 * A DMA channel begins processing commands when its hardware semaphore is
460 * written with a value greater than zero, and it stops processing commands
461 * when the semaphore returns to zero.
463 * When a channel finishes a DMA command, it will decrement its semaphore if
464 * the DECREMENT_SEMAPHORE bit is set in that command's flags bits.
466 * In principle, it's not necessary for the DECREMENT_SEMAPHORE to be set,
467 * unless it suits the purposes of the software. For example, one could
468 * construct a series of five DMA commands, with the DECREMENT_SEMAPHORE
469 * bit set only in the last one. Then, setting the DMA channel's hardware
470 * semaphore to one would cause the entire series of five commands to be
471 * processed. However, this example would violate the invariant given above.
474 * ALL DMA commands MUST have the DECREMENT_SEMAPHORE bit set so that the DMA
475 * channel's hardware semaphore will be decremented EVERY time a command is
478 int mxs_dma_desc_append(int channel, struct mxs_dma_desc *pdesc)
480 struct mxs_dma_chan *pchan;
481 struct mxs_dma_desc *last;
484 ret = mxs_dma_validate_chan(channel);
488 pchan = mxs_dma_channels + channel;
490 pdesc->cmd.next = mxs_dma_cmd_address(pdesc);
491 pdesc->flags |= MXS_DMA_DESC_FIRST | MXS_DMA_DESC_LAST;
493 if (!list_empty(&pchan->active)) {
494 last = list_entry(pchan->active.prev, struct mxs_dma_desc,
497 pdesc->flags &= ~MXS_DMA_DESC_FIRST;
498 last->flags &= ~MXS_DMA_DESC_LAST;
500 last->cmd.next = mxs_dma_cmd_address(pdesc);
501 last->cmd.data |= MXS_DMA_DESC_CHAIN;
503 pdesc->flags |= MXS_DMA_DESC_READY;
504 if (pdesc->flags & MXS_DMA_DESC_FIRST)
505 pchan->pending_num++;
506 list_add_tail(&pdesc->node, &pchan->active);
512 * Retrieve processed DMA descriptors.
514 * This function moves all the descriptors from the DMA channel's "done" list to
515 * the head of the given list.
517 int mxs_dma_get_finished(int channel, struct list_head *head)
519 struct mxs_dma_chan *pchan;
522 ret = mxs_dma_validate_chan(channel);
529 pchan = mxs_dma_channels + channel;
531 list_splice(&pchan->done, head);
537 * Clean up processed DMA descriptors.
539 * This function removes processed DMA descriptors from the "active" list. Pass
540 * in a non-NULL list head to get the descriptors moved to your list. Pass NULL
541 * to get the descriptors moved to the channel's "done" list. Descriptors on
542 * the "done" list can be retrieved with mxs_dma_get_finished().
544 * This function marks the DMA channel as "not busy" if no unprocessed
545 * descriptors remain on the "active" list.
547 int mxs_dma_finish(int channel, struct list_head *head)
550 struct mxs_dma_chan *pchan;
551 struct list_head *p, *q;
552 struct mxs_dma_desc *pdesc;
555 ret = mxs_dma_validate_chan(channel);
559 pchan = mxs_dma_channels + channel;
561 sem = mxs_dma_read_semaphore(channel);
565 if (sem == pchan->active_num)
568 list_for_each_safe(p, q, &pchan->active) {
569 if ((pchan->active_num) <= sem)
572 pdesc = list_entry(p, struct mxs_dma_desc, node);
573 pdesc->flags &= ~MXS_DMA_DESC_READY;
576 list_move_tail(p, head);
578 list_move_tail(p, &pchan->done);
580 if (pdesc->flags & MXS_DMA_DESC_LAST)
585 pchan->flags &= ~MXS_DMA_FLAGS_BUSY;
591 * Wait for DMA channel to complete
593 int mxs_dma_wait_complete(uint32_t timeout, unsigned int chan)
595 struct mx28_apbh_regs *apbh_regs =
596 (struct mx28_apbh_regs *)MXS_APBH_BASE;
599 ret = mxs_dma_validate_chan(chan);
603 if (mx28_wait_mask_set(&apbh_regs->hw_apbh_ctrl1_reg,
604 1 << chan, timeout)) {
613 * Execute the DMA channel
615 int mxs_dma_go(int chan)
617 uint32_t timeout = 10000;
620 LIST_HEAD(tmp_desc_list);
622 mxs_dma_enable_irq(chan, 1);
623 mxs_dma_enable(chan);
625 /* Wait for DMA to finish. */
626 ret = mxs_dma_wait_complete(timeout, chan);
628 /* Clear out the descriptors we just ran. */
629 mxs_dma_finish(chan, &tmp_desc_list);
631 /* Shut the DMA channel down. */
632 mxs_dma_ack_irq(chan);
634 mxs_dma_enable_irq(chan, 0);
635 mxs_dma_disable(chan);
641 * Initialize the DMA hardware
643 int mxs_dma_init(void)
645 struct mx28_apbh_regs *apbh_regs =
646 (struct mx28_apbh_regs *)MXS_APBH_BASE;
647 struct mxs_dma_chan *pchan;
650 mx28_reset_block(&apbh_regs->hw_apbh_ctrl0_reg);
652 #ifdef CONFIG_APBH_DMA_BURST8
653 writel(APBH_CTRL0_AHB_BURST8_EN,
654 &apbh_regs->hw_apbh_ctrl0_set);
656 writel(APBH_CTRL0_AHB_BURST8_EN,
657 &apbh_regs->hw_apbh_ctrl0_clr);
660 #ifdef CONFIG_APBH_DMA_BURST
661 writel(APBH_CTRL0_APB_BURST_EN,
662 &apbh_regs->hw_apbh_ctrl0_set);
664 writel(APBH_CTRL0_APB_BURST_EN,
665 &apbh_regs->hw_apbh_ctrl0_clr);
668 for (channel = 0; channel < MXS_MAX_DMA_CHANNELS; channel++) {
669 pchan = mxs_dma_channels + channel;
670 pchan->flags = MXS_DMA_FLAGS_VALID;
672 ret = mxs_dma_request(channel);
675 printf("MXS DMA: Can't acquire DMA channel %i\n",
681 mxs_dma_reset(channel);
682 mxs_dma_ack_irq(channel);
688 while (--channel >= 0)
689 mxs_dma_release(channel);