2 * Copyright 2004,2007,2008 Freescale Semiconductor, Inc.
3 * (C) Copyright 2002, 2003 Motorola Inc.
4 * Xianghua Xiao (X.Xiao@motorola.com)
7 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
9 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/fsl_dma.h>
17 /* Controller can only transfer 2^26 - 1 bytes at a time */
18 #define FSL_DMA_MAX_SIZE (0x3ffffff)
20 #if defined(CONFIG_MPC83xx)
21 #define FSL_DMA_MR_DEFAULT (FSL_DMA_MR_CTM_DIRECT | FSL_DMA_MR_DMSEN)
23 #define FSL_DMA_MR_DEFAULT (FSL_DMA_MR_BWC_DIS | FSL_DMA_MR_CTM_DIRECT)
27 #if defined(CONFIG_MPC83xx)
28 dma83xx_t *dma_base = (void *)(CONFIG_SYS_MPC83xx_DMA_ADDR);
29 #elif defined(CONFIG_MPC85xx)
30 ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
31 #elif defined(CONFIG_MPC86xx)
32 ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
34 #error "Freescale DMA engine not supported on your processor"
37 static void dma_sync(void)
39 #if defined(CONFIG_MPC85xx)
40 asm("sync; isync; msync");
41 #elif defined(CONFIG_MPC86xx)
46 static void out_dma32(volatile unsigned *addr, int val)
48 #if defined(CONFIG_MPC83xx)
55 static uint in_dma32(volatile unsigned *addr)
57 #if defined(CONFIG_MPC83xx)
64 static uint dma_check(void) {
65 volatile fsl_dma_t *dma = &dma_base->dma[0];
68 /* While the channel is busy, spin */
70 status = in_dma32(&dma->sr);
71 } while (status & FSL_DMA_SR_CB);
73 /* clear MR[CS] channel start bit */
74 out_dma32(&dma->mr, in_dma32(&dma->mr) & ~FSL_DMA_MR_CS);
78 printf ("DMA Error: status = %x\n", status);
83 #if !defined(CONFIG_MPC83xx)
85 volatile fsl_dma_t *dma = &dma_base->dma[0];
87 out_dma32(&dma->satr, FSL_DMA_SATR_SREAD_SNOOP);
88 out_dma32(&dma->datr, FSL_DMA_DATR_DWRITE_SNOOP);
89 out_dma32(&dma->sr, 0xffffffff); /* clear any errors */
94 int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t count) {
95 volatile fsl_dma_t *dma = &dma_base->dma[0];
99 xfer_size = min(FSL_DMA_MAX_SIZE, count);
101 out_dma32(&dma->dar, (u32) (dest & 0xFFFFFFFF));
102 out_dma32(&dma->sar, (u32) (src & 0xFFFFFFFF));
103 #if !defined(CONFIG_MPC83xx)
104 out_dma32(&dma->satr,
105 in_dma32(&dma->satr) | (u32)((u64)src >> 32));
106 out_dma32(&dma->datr,
107 in_dma32(&dma->datr) | (u32)((u64)dest >> 32));
109 out_dma32(&dma->bcr, xfer_size);
112 /* Prepare mode register */
113 out_dma32(&dma->mr, FSL_DMA_MR_DEFAULT);
116 /* Start the transfer */
117 out_dma32(&dma->mr, FSL_DMA_MR_DEFAULT | FSL_DMA_MR_CS);
133 * 85xx/86xx use dma to initialize SDRAM when !CONFIG_ECC_INIT_VIA_DDRCONTROLLER
134 * while 83xx uses dma to initialize SDRAM when CONFIG_DDR_ECC_INIT_VIA_DMA
136 #if ((!defined CONFIG_MPC83xx && defined(CONFIG_DDR_ECC) && \
137 !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) || \
138 (defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)))
139 void dma_meminit(uint val, uint size)
144 for (*p = 0; p < (uint *)(8 * 1024); p++) {
145 if (((uint)p & 0x1f) == 0)
148 *p = (uint)CONFIG_MEM_INIT_VALUE;
150 if (((uint)p & 0x1c) == 0x1c)
154 dmacpy(0x002000, 0, 0x002000); /* 8K */
155 dmacpy(0x004000, 0, 0x004000); /* 16K */
156 dmacpy(0x008000, 0, 0x008000); /* 32K */
157 dmacpy(0x010000, 0, 0x010000); /* 64K */
158 dmacpy(0x020000, 0, 0x020000); /* 128K */
159 dmacpy(0x040000, 0, 0x040000); /* 256K */
160 dmacpy(0x080000, 0, 0x080000); /* 512K */
161 dmacpy(0x100000, 0, 0x100000); /* 1M */
162 dmacpy(0x200000, 0, 0x200000); /* 2M */
163 dmacpy(0x400000, 0, 0x400000); /* 4M */
165 for (i = 1; i < size / 0x800000; i++)
166 dmacpy((0x800000 * i), 0, 0x800000);