2 * Copyright (C) 2008 by NXP Semiconductors
4 * @Descr: LPC3250 DMA controller interface support functions
6 * Copyright (c) 2015 Tyco Fire Protection Products.
8 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/dma.h>
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/clk.h>
16 #include <asm/arch/sys_proto.h>
19 /* DMA controller channel register structure */
20 struct dmac_chan_reg {
29 /* DMA controller register structures */
41 u32 sw_last_burst_req;
42 u32 sw_last_single_req;
46 struct dmac_chan_reg dma_chan[8];
49 #define DMA_NO_OF_CHANNELS 8
51 /* config register definitions */
52 #define DMAC_CTRL_ENABLE (1 << 0) /* For enabling the DMA controller */
56 static struct dma_reg *dma = (struct dma_reg *)DMA_BASE;
58 int lpc32xx_dma_get_channel(void)
62 if (!alloc_ch) { /* First time caller */
64 * DMA clock are enable by "lpc32xx_dma_init()" and should
65 * be call by board "board_early_init_f()" function.
69 * Make sure DMA controller and all channels are disabled.
70 * Controller is in little-endian mode. Disable sync signals.
72 writel(0, &dma->config);
73 writel(0, &dma->sync);
75 /* Clear interrupt and error statuses */
76 writel(0xFF, &dma->int_tc_clear);
77 writel(0xFF, &dma->raw_tc_stat);
78 writel(0xFF, &dma->int_err_clear);
79 writel(0xFF, &dma->raw_err_stat);
81 /* Enable DMA controller */
82 writel(DMAC_CTRL_ENABLE, &dma->config);
87 /* Check if all the available channels are busy */
88 if (unlikely(i == DMA_NO_OF_CHANNELS))
90 alloc_ch |= BIT_MASK(i);
94 int lpc32xx_dma_start_xfer(unsigned int channel,
95 const struct lpc32xx_dmac_ll *desc, u32 config)
97 if (unlikely(((BIT_MASK(channel) & alloc_ch) == 0) ||
98 (channel >= DMA_NO_OF_CHANNELS))) {
99 error("Request for xfer on unallocated channel %d", channel);
102 writel(BIT_MASK(channel), &dma->int_tc_clear);
103 writel(BIT_MASK(channel), &dma->int_err_clear);
104 writel(desc->dma_src, &dma->dma_chan[channel].src_addr);
105 writel(desc->dma_dest, &dma->dma_chan[channel].dest_addr);
106 writel(desc->next_lli, &dma->dma_chan[channel].lli);
107 writel(desc->next_ctrl, &dma->dma_chan[channel].control);
108 writel(config, &dma->dma_chan[channel].config_ch);
113 int lpc32xx_dma_wait_status(unsigned int channel)
118 /* Check if given channel is valid */
119 if (unlikely(channel >= DMA_NO_OF_CHANNELS)) {
120 error("Request for status on unallocated channel %d", channel);
124 start = get_timer(0);
126 reg = readl(&dma->raw_tc_stat);
127 reg |= readl(dma->raw_err_stat);
128 if (reg & BIT_MASK(channel))
131 if (get_timer(start) > CONFIG_SYS_HZ) {
132 error("DMA status timeout channel %d\n", channel);
138 if (unlikely(readl(&dma->raw_err_stat) & BIT_MASK(channel))) {
139 setbits_le32(&dma->int_err_clear, BIT_MASK(channel));
140 setbits_le32(&dma->raw_err_stat, BIT_MASK(channel));
141 error("DMA error on channel %d\n", channel);
144 setbits_le32(&dma->int_tc_clear, BIT_MASK(channel));
145 setbits_le32(&dma->raw_tc_stat, BIT_MASK(channel));