2 * Copyright (C) 2017 Intel Corporation <www.intel.com>
4 * SPDX-License-Identifier: GPL-2.0
8 #include <asm/arch/fpga_manager.h>
9 #include <asm/arch/reset_manager.h>
10 #include <asm/arch/system_manager.h>
11 #include <asm/arch/sdram.h>
12 #include <asm/arch/misc.h>
20 #define MIN_BITSTREAM_SIZECHECK 230
21 #define ENCRYPTION_OFFSET 69
22 #define COMPRESSION_OFFSET 229
23 #define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */
24 #define FPGA_TIMEOUT_CNT 0x1000000
26 static const struct socfpga_fpga_manager *fpga_manager_base =
27 (void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
29 static const struct socfpga_system_manager *system_manager_base =
30 (void *)SOCFPGA_SYSMGR_ADDRESS;
32 static void fpgamgr_set_cd_ratio(unsigned long ratio);
34 static uint32_t fpgamgr_get_msel(void)
38 reg = readl(&fpga_manager_base->imgcfg_stat);
39 reg = (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD) >>
40 ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB;
45 static void fpgamgr_set_cfgwdth(int width)
48 setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
49 ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
51 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
52 ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
55 int is_fpgamgr_user_mode(void)
57 return (readl(&fpga_manager_base->imgcfg_stat) &
58 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) != 0;
61 static int wait_for_user_mode(void)
63 return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
64 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK,
65 1, FPGA_TIMEOUT_MSEC, false);
68 static int is_fpgamgr_early_user_mode(void)
70 return (readl(&fpga_manager_base->imgcfg_stat) &
71 ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0;
74 int fpgamgr_wait_early_user_mode(void)
76 u32 sync_data = 0xffffffff;
78 unsigned start = get_timer(0);
79 unsigned long cd_ratio;
81 /* Getting existing CDRATIO */
82 cd_ratio = (readl(&fpga_manager_base->imgcfg_ctrl_02) &
83 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK) >>
84 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB;
86 /* Using CDRATIO_X1 for better compatibility */
87 fpgamgr_set_cd_ratio(CDRATIO_x1);
89 while (!is_fpgamgr_early_user_mode()) {
90 if (get_timer(start) > FPGA_TIMEOUT_MSEC)
92 fpgamgr_program_write((const long unsigned int *)&sync_data,
94 udelay(FPGA_TIMEOUT_MSEC);
98 debug("Additional %i sync word needed\n", i);
100 /* restoring original CDRATIO */
101 fpgamgr_set_cd_ratio(cd_ratio);
106 /* Read f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted */
107 static int wait_for_nconfig_pin_and_nstatus_pin(void)
109 unsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
110 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK;
113 * Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until
114 * de-asserted, timeout at 1000ms
116 return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat, mask,
117 true, FPGA_TIMEOUT_MSEC, false);
120 static int wait_for_f2s_nstatus_pin(unsigned long value)
122 /* Poll until f2s to specific value, timeout at 1000ms */
123 return wait_for_bit_le32(&fpga_manager_base->imgcfg_stat,
124 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK,
125 value, FPGA_TIMEOUT_MSEC, false);
129 static void fpgamgr_set_cd_ratio(unsigned long ratio)
131 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
132 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
134 setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
135 (ratio << ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB) &
136 ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
139 /* get the MSEL value, verify we are set for FPP configuration mode */
140 static int fpgamgr_verify_msel(void)
142 u32 msel = fpgamgr_get_msel();
144 if (msel & ~BIT(0)) {
145 printf("Fail: read msel=%d\n", msel);
153 * Write cdratio and cdwidth based on whether the bitstream is compressed
156 static int fpgamgr_set_cdratio_cdwidth(unsigned int cfg_width, u32 *rbf_data,
159 unsigned int cd_ratio;
160 bool encrypt, compress;
163 * According to the bitstream specification,
164 * both encryption and compression status are
165 * in location before offset 230 of the buffer.
167 if (rbf_size < MIN_BITSTREAM_SIZECHECK)
170 encrypt = (rbf_data[ENCRYPTION_OFFSET] >> 2) & 3;
171 encrypt = encrypt != 0;
173 compress = (rbf_data[COMPRESSION_OFFSET] >> 1) & 1;
174 compress = !compress;
176 debug("header word %d = %08x\n", 69, rbf_data[69]);
177 debug("header word %d = %08x\n", 229, rbf_data[229]);
178 debug("read from rbf header: encrypt=%d compress=%d\n", encrypt, compress);
181 * from the register map description of cdratio in imgcfg_ctrl_02:
182 * Normal Configuration : 32bit Passive Parallel
183 * Partial Reconfiguration : 16bit Passive Parallel
187 * cd ratio is dependent on cfg width and whether the bitstream
188 * is encrypted and/or compressed.
190 * | width | encr. | compr. | cd ratio |
200 if (!compress && !encrypt) {
201 cd_ratio = CDRATIO_x1;
204 cd_ratio = CDRATIO_x4;
206 cd_ratio = CDRATIO_x2;
208 /* if 32 bit, double the cd ratio (so register
209 field setting is incremented) */
210 if (cfg_width == CFGWDTH_32)
214 fpgamgr_set_cfgwdth(cfg_width);
215 fpgamgr_set_cd_ratio(cd_ratio);
220 static int fpgamgr_reset(void)
224 /* S2F_NCONFIG = 0 */
225 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
226 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
228 /* Wait for f2s_nstatus == 0 */
229 if (wait_for_f2s_nstatus_pin(0))
232 /* S2F_NCONFIG = 1 */
233 setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
234 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
236 /* Wait for f2s_nstatus == 1 */
237 if (wait_for_f2s_nstatus_pin(1))
240 /* read and confirm f2s_condone_pin = 0 and f2s_condone_oe = 1 */
241 reg = readl(&fpga_manager_base->imgcfg_stat);
242 if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) != 0)
245 if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_OE_SET_MSK) == 0)
251 /* Start the FPGA programming by initialize the FPGA Manager */
252 int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size)
257 if (fpgamgr_verify_msel())
261 if (fpgamgr_set_cdratio_cdwidth(CFGWDTH_32, rbf_data, rbf_size))
266 * Make sure no other external devices are trying to interfere with
269 if (wait_for_nconfig_pin_and_nstatus_pin())
274 * Deassert the signal drives from HPS
284 setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
285 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
287 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
288 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_PR_REQUEST_SET_MSK);
290 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
291 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
292 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
294 setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
295 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NCONFIG_SET_MSK);
297 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
298 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NSTATUS_OE_SET_MSK |
299 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_CONDONE_OE_SET_MSK);
304 * S2F_NENABLE_CONFIG = 0
305 * S2F_NENABLE_NCONFIG = 0
307 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
308 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
309 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
310 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
313 * Disable driving signals that HPS doesn't need to drive.
314 * S2F_NENABLE_NSTATUS = 1
315 * S2F_NENABLE_CONDONE = 1
317 setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
318 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NSTATUS_SET_MSK |
319 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_CONDONE_SET_MSK);
323 * Drive chip select S2F_NCE = 0
325 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
326 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
329 if (wait_for_nconfig_pin_and_nstatus_pin())
333 ret = fpgamgr_reset();
340 * EN_CFG_CTRL and EN_CFG_DATA = 1
342 setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
343 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
344 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
349 /* Ensure the FPGA entering config done */
350 static int fpgamgr_program_poll_cd(void)
352 unsigned long reg, i;
354 for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
355 reg = readl(&fpga_manager_base->imgcfg_stat);
356 if (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK)
359 if ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) == 0) {
360 printf("nstatus == 0 while waiting for condone\n");
365 if (i == FPGA_TIMEOUT_CNT)
371 /* Ensure the FPGA entering user mode */
372 static int fpgamgr_program_poll_usermode(void)
377 if (fpgamgr_dclkcnt_set(0xf))
380 ret = wait_for_user_mode();
382 printf("%s: Failed to enter user mode with ", __func__);
383 printf("error code %d\n", ret);
389 * Stop DATA path and Dclk
390 * EN_CFG_CTRL and EN_CFG_DATA = 0
392 clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
393 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_DATA_SET_MSK |
394 ALT_FPGAMGR_IMGCFG_CTL_02_EN_CFG_CTRL_SET_MSK);
399 * S2F_NENABLE_CONFIG = 1
400 * S2F_NENABLE_NCONFIG = 1
402 setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
403 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NENABLE_CONFIG_SET_MSK);
404 setbits_le32(&fpga_manager_base->imgcfg_ctrl_00,
405 ALT_FPGAMGR_IMGCFG_CTL_00_S2F_NENABLE_NCONFIG_SET_MSK);
407 /* Disable chip select S2F_NCE = 1 */
408 setbits_le32(&fpga_manager_base->imgcfg_ctrl_01,
409 ALT_FPGAMGR_IMGCFG_CTL_01_S2F_NCE_SET_MSK);
415 reg = readl(&fpga_manager_base->imgcfg_stat);
416 if (((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) !=
417 ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) ||
418 ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) !=
419 ALT_FPGAMGR_IMGCFG_STAT_F2S_CONDONE_PIN_SET_MSK) ||
420 ((reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK) !=
421 ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK))
427 int fpgamgr_program_finish(void)
429 /* Ensure the FPGA entering config done */
430 int status = fpgamgr_program_poll_cd();
433 printf("FPGA: Poll CD failed with error code %d\n", status);
438 /* Ensure the FPGA entering user mode */
439 status = fpgamgr_program_poll_usermode();
441 printf("FPGA: Poll usermode failed with error code %d\n",
446 printf("Full Configuration Succeeded.\n");
452 * FPGA Manager to program the FPGA. This is the interface used by FPGA driver.
453 * Return 0 for sucess, non-zero for error.
455 int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
457 unsigned long status;
459 /* disable all signals from hps peripheral controller to fpga */
460 writel(0, &system_manager_base->fpgaintf_en_global);
462 /* disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
463 socfpga_bridges_reset();
465 /* Initialize the FPGA Manager */
466 status = fpgamgr_program_init((u32 *)rbf_data, rbf_size);
470 /* Write the RBF data to FPGA Manager */
471 fpgamgr_program_write(rbf_data, rbf_size);
473 return fpgamgr_program_finish();