2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
5 * SPDX-License-Identifier: BSD-3-Clause
10 #include <linux/errno.h>
11 #include <asm/arch/fpga_manager.h>
12 #include <asm/arch/reset_manager.h>
13 #include <asm/arch/system_manager.h>
15 DECLARE_GLOBAL_DATA_PTR;
17 #define FPGA_TIMEOUT_CNT 0x1000000
19 static struct socfpga_fpga_manager *fpgamgr_regs =
20 (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
21 static struct socfpga_system_manager *sysmgr_regs =
22 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
25 static void fpgamgr_set_cd_ratio(unsigned long ratio)
27 clrsetbits_le32(&fpgamgr_regs->ctrl,
28 0x3 << FPGAMGRREGS_CTRL_CDRATIO_LSB,
29 (ratio & 0x3) << FPGAMGRREGS_CTRL_CDRATIO_LSB);
32 /* Start the FPGA programming by initialize the FPGA Manager */
33 static int fpgamgr_program_init(void)
35 unsigned long msel, i;
37 /* Get the MSEL value */
38 msel = readl(&fpgamgr_regs->stat);
39 msel &= FPGAMGRREGS_STAT_MSEL_MASK;
40 msel >>= FPGAMGRREGS_STAT_MSEL_LSB;
44 * If MSEL[3] = 1, cfg width = 32 bit
47 setbits_le32(&fpgamgr_regs->ctrl,
48 FPGAMGRREGS_CTRL_CFGWDTH_MASK);
50 /* To determine the CD ratio */
51 /* MSEL[1:0] = 0, CD Ratio = 1 */
52 if ((msel & 0x3) == 0x0)
53 fpgamgr_set_cd_ratio(CDRATIO_x1);
54 /* MSEL[1:0] = 1, CD Ratio = 4 */
55 else if ((msel & 0x3) == 0x1)
56 fpgamgr_set_cd_ratio(CDRATIO_x4);
57 /* MSEL[1:0] = 2, CD Ratio = 8 */
58 else if ((msel & 0x3) == 0x2)
59 fpgamgr_set_cd_ratio(CDRATIO_x8);
61 } else { /* MSEL[3] = 0 */
62 clrbits_le32(&fpgamgr_regs->ctrl,
63 FPGAMGRREGS_CTRL_CFGWDTH_MASK);
65 /* To determine the CD ratio */
66 /* MSEL[1:0] = 0, CD Ratio = 1 */
67 if ((msel & 0x3) == 0x0)
68 fpgamgr_set_cd_ratio(CDRATIO_x1);
69 /* MSEL[1:0] = 1, CD Ratio = 2 */
70 else if ((msel & 0x3) == 0x1)
71 fpgamgr_set_cd_ratio(CDRATIO_x2);
72 /* MSEL[1:0] = 2, CD Ratio = 4 */
73 else if ((msel & 0x3) == 0x2)
74 fpgamgr_set_cd_ratio(CDRATIO_x4);
77 /* To enable FPGA Manager configuration */
78 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCE_MASK);
80 /* To enable FPGA Manager drive over configuration line */
81 setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK);
83 /* Put FPGA into reset phase */
84 setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK);
86 /* (1) wait until FPGA enter reset phase */
87 for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
88 if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_RESETPHASE)
92 /* If not in reset state, return error */
93 if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_RESETPHASE) {
94 puts("FPGA: Could not reset\n");
98 /* Release FPGA from reset phase */
99 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_NCONFIGPULL_MASK);
101 /* (2) wait until FPGA enter configuration phase */
102 for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
103 if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_CFGPHASE)
107 /* If not in configuration state, return error */
108 if (fpgamgr_get_mode() != FPGAMGRREGS_MODE_CFGPHASE) {
109 puts("FPGA: Could not configure\n");
113 /* Clear all interrupts in CB Monitor */
114 writel(0xFFF, &fpgamgr_regs->gpio_porta_eoi);
116 /* Enable AXI configuration */
117 setbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK);
122 /* Ensure the FPGA entering config done */
123 static int fpgamgr_program_poll_cd(void)
125 const uint32_t mask = FPGAMGRREGS_MON_GPIO_EXT_PORTA_NS_MASK |
126 FPGAMGRREGS_MON_GPIO_EXT_PORTA_CD_MASK;
127 unsigned long reg, i;
129 /* (3) wait until full config done */
130 for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
131 reg = readl(&fpgamgr_regs->gpio_ext_porta);
135 printf("FPGA: Configuration error.\n");
139 /* Config done without error */
144 /* Timeout happened, return error */
145 if (i == FPGA_TIMEOUT_CNT) {
146 printf("FPGA: Timeout waiting for program.\n");
150 /* Disable AXI configuration */
151 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_AXICFGEN_MASK);
156 /* Ensure the FPGA entering init phase */
157 static int fpgamgr_program_poll_initphase(void)
161 /* Additional clocks for the CB to enter initialization phase */
162 if (fpgamgr_dclkcnt_set(0x4))
165 /* (4) wait until FPGA enter init phase or user mode */
166 for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
167 if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_INITPHASE)
169 if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE)
173 /* If not in configuration state, return error */
174 if (i == FPGA_TIMEOUT_CNT)
180 /* Ensure the FPGA entering user mode */
181 static int fpgamgr_program_poll_usermode(void)
185 /* Additional clocks for the CB to exit initialization phase */
186 if (fpgamgr_dclkcnt_set(0x5000))
189 /* (5) wait until FPGA enter user mode */
190 for (i = 0; i < FPGA_TIMEOUT_CNT; i++) {
191 if (fpgamgr_get_mode() == FPGAMGRREGS_MODE_USERMODE)
194 /* If not in configuration state, return error */
195 if (i == FPGA_TIMEOUT_CNT)
198 /* To release FPGA Manager drive over configuration line */
199 clrbits_le32(&fpgamgr_regs->ctrl, FPGAMGRREGS_CTRL_EN_MASK);
205 * FPGA Manager to program the FPGA. This is the interface used by FPGA driver.
206 * Return 0 for sucess, non-zero for error.
208 int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
210 unsigned long status;
212 if ((uint32_t)rbf_data & 0x3) {
213 puts("FPGA: Unaligned data, realign to 32bit boundary.\n");
217 /* Prior programming the FPGA, all bridges need to be shut off */
219 /* Disable all signals from hps peripheral controller to fpga */
220 writel(0, &sysmgr_regs->fpgaintfgrp_module);
222 /* Disable all signals from FPGA to HPS SDRAM */
223 #define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080
224 writel(0, SOCFPGA_SDR_ADDRESS + SDR_CTRLGRP_FPGAPORTRST_ADDRESS);
226 /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */
227 socfpga_bridges_reset(1);
229 /* Unmap the bridges from NIC-301 */
230 writel(0x1, SOCFPGA_L3REGS_ADDRESS);
232 /* Initialize the FPGA Manager */
233 status = fpgamgr_program_init();
237 /* Write the RBF data to FPGA Manager */
238 fpgamgr_program_write(rbf_data, rbf_size);
240 /* Ensure the FPGA entering config done */
241 status = fpgamgr_program_poll_cd();
245 /* Ensure the FPGA entering init phase */
246 status = fpgamgr_program_poll_initphase();
250 /* Ensure the FPGA entering user mode */
251 return fpgamgr_program_poll_usermode();