2 * Copyright (C) 2016 Stefan Roese <sr@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
11 #include <linux/errno.h>
13 /* Write the RBF data to FPGA via SPI */
14 static int program_write(int spi_bus, int spi_dev, const void *rbf_data,
15 unsigned long rbf_size)
17 struct spi_slave *slave;
20 debug("%s (%d): data=%p size=%ld\n",
21 __func__, __LINE__, rbf_data, rbf_size);
23 /* FIXME: How to get the max. SPI clock and SPI mode? */
24 slave = spi_setup_slave(spi_bus, spi_dev, 27777777, SPI_MODE_3);
28 if (spi_claim_bus(slave))
31 ret = spi_xfer(slave, rbf_size * 8, rbf_data, (void *)rbf_data,
32 SPI_XFER_BEGIN | SPI_XFER_END);
34 spi_release_bus(slave);
40 * This is the interface used by FPGA driver.
41 * Return 0 for sucess, non-zero for error.
43 int stratixv_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
45 altera_board_specific_func *pfns = desc->iface_fns;
46 int cookie = desc->cookie;
51 if ((u32)rbf_data & 0x3) {
52 puts("FPGA: Unaligned data, realign to 32bit boundary.\n");
56 /* Run the pre configuration function if there is one */
60 /* Establish the initial state */
62 /* De-assert nCONFIG */
63 (pfns->config)(false, true, cookie);
65 /* nConfig minimum low pulse width is 2us */
69 (pfns->config)(true, true, cookie);
71 /* nCONFIG high to first rising clock on DCLK min 1506 us */
75 /* Write the RBF data to FPGA */
78 * Use board specific data function to write bitstream
81 ret = (pfns->write)(rbf_data, rbf_size, true, cookie);
84 * Use common SPI functions to write bitstream into the
87 spi_bus = COOKIE2SPI_BUS(cookie);
88 spi_dev = COOKIE2SPI_DEV(cookie);
89 ret = program_write(spi_bus, spi_dev, rbf_data, rbf_size);
96 ret = (pfns->done)(cookie);
99 printf("Error: DONE not set (ret=%d)!\n", ret);