2 * (C) Copyright 2012-2013, Xilinx, Michal Simek
5 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
6 * Keith Outwater, keith_outwater@mvis.com
8 * SPDX-License-Identifier: GPL-2.0+
22 /* Local Static Functions */
23 static int xilinx_validate(xilinx_desc *desc, char *fn);
25 /* ------------------------------------------------------------------------- */
27 int fpga_is_partial_data(int devnum, size_t img_len)
29 const fpga_desc * const desc = fpga_get_desc(devnum);
30 xilinx_desc *desc_xilinx = desc->devdesc;
32 /* Check datasize against FPGA size */
33 if (img_len >= desc_xilinx->size)
36 /* datasize is smaller, must be partial data */
40 int fpga_loadbitstream(int devnum, char *fpgadata, size_t size,
41 bitstream_type bstype)
44 unsigned int swapsize;
45 unsigned char *dataptr;
47 const fpga_desc *desc;
50 dataptr = (unsigned char *)fpgadata;
51 /* Find out fpga_description */
52 desc = fpga_validate(devnum, dataptr, 0, (char *)__func__);
53 /* Assign xilinx device description */
54 xdesc = desc->devdesc;
56 /* skip the first bytes of the bitsteam, their meaning is unknown */
57 length = (*dataptr << 8) + *(dataptr + 1);
61 /* get design name (identifier, length, string) */
62 length = (*dataptr << 8) + *(dataptr + 1);
64 if (*dataptr++ != 0x61) {
65 debug("%s: Design name id not recognized in bitstream\n",
70 length = (*dataptr << 8) + *(dataptr + 1);
72 printf(" design filename = \"%s\"\n", dataptr);
75 /* get part number (identifier, length, string) */
76 if (*dataptr++ != 0x62) {
77 printf("%s: Part number id not recognized in bitstream\n",
82 length = (*dataptr << 8) + *(dataptr + 1);
86 i = (ulong)strstr((char *)dataptr, xdesc->name);
88 printf("%s: Wrong bitstream ID for this device\n",
90 printf("%s: Bitstream ID %s, current device ID %d/%s\n",
91 __func__, dataptr, devnum, xdesc->name);
95 printf("%s: Please fill correct device ID to xilinx_desc\n",
98 printf(" part number = \"%s\"\n", dataptr);
101 /* get date (identifier, length, string) */
102 if (*dataptr++ != 0x63) {
103 printf("%s: Date identifier not recognized in bitstream\n",
108 length = (*dataptr << 8) + *(dataptr+1);
110 printf(" date = \"%s\"\n", dataptr);
113 /* get time (identifier, length, string) */
114 if (*dataptr++ != 0x64) {
115 printf("%s: Time identifier not recognized in bitstream\n",
120 length = (*dataptr << 8) + *(dataptr+1);
122 printf(" time = \"%s\"\n", dataptr);
125 /* get fpga data length (identifier, length) */
126 if (*dataptr++ != 0x65) {
127 printf("%s: Data length id not recognized in bitstream\n",
131 swapsize = ((unsigned int) *dataptr << 24) +
132 ((unsigned int) *(dataptr + 1) << 16) +
133 ((unsigned int) *(dataptr + 2) << 8) +
134 ((unsigned int) *(dataptr + 3));
136 printf(" bytes in bitstream = %d\n", swapsize);
138 return fpga_load(devnum, dataptr, swapsize, bstype);
141 int xilinx_load(xilinx_desc *desc, const void *buf, size_t bsize,
142 bitstream_type bstype)
144 if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
145 printf ("%s: Invalid device descriptor\n", __FUNCTION__);
149 if (!desc->operations || !desc->operations->load) {
150 printf("%s: Missing load operation\n", __func__);
154 return desc->operations->load(desc, buf, bsize, bstype);
157 #if defined(CONFIG_CMD_FPGA_LOADFS)
158 int xilinx_loadfs(xilinx_desc *desc, const void *buf, size_t bsize,
159 fpga_fs_info *fpga_fsinfo)
161 if (!xilinx_validate(desc, (char *)__func__)) {
162 printf("%s: Invalid device descriptor\n", __func__);
166 if (!desc->operations || !desc->operations->loadfs) {
167 printf("%s: Missing loadfs operation\n", __func__);
171 return desc->operations->loadfs(desc, buf, bsize, fpga_fsinfo);
175 int xilinx_dump(xilinx_desc *desc, const void *buf, size_t bsize)
177 if (!xilinx_validate (desc, (char *)__FUNCTION__)) {
178 printf ("%s: Invalid device descriptor\n", __FUNCTION__);
182 if (!desc->operations || !desc->operations->dump) {
183 printf("%s: Missing dump operation\n", __func__);
187 return desc->operations->dump(desc, buf, bsize);
190 int xilinx_info(xilinx_desc *desc)
192 int ret_val = FPGA_FAIL;
194 if (xilinx_validate (desc, (char *)__FUNCTION__)) {
195 printf ("Family: \t");
196 switch (desc->family) {
197 case xilinx_spartan2:
198 printf ("Spartan-II\n");
200 case xilinx_spartan3:
201 printf ("Spartan-III\n");
204 printf ("Virtex-II\n");
210 printf("ZynqMP PL\n");
212 /* Add new family types here */
214 printf ("Unknown family type, %d\n", desc->family);
217 printf ("Interface type:\t");
218 switch (desc->iface) {
220 printf ("Slave Serial\n");
222 case master_serial: /* Not used */
223 printf ("Master Serial\n");
226 printf ("Slave Parallel\n");
228 case jtag_mode: /* Not used */
229 printf ("JTAG Mode\n");
231 case slave_selectmap:
232 printf ("Slave SelectMap Mode\n");
234 case master_selectmap:
235 printf ("Master SelectMap Mode\n");
238 printf("Device configuration interface (Zynq)\n");
241 printf("csu_dma configuration interface (ZynqMP)\n");
243 /* Add new interface types here */
245 printf ("Unsupported interface type, %d\n", desc->iface);
248 printf("Device Size: \t%zd bytes\n"
249 "Cookie: \t0x%x (%d)\n",
250 desc->size, desc->cookie, desc->cookie);
252 printf("Device name: \t%s\n", desc->name);
255 printf ("Device Function Table @ 0x%p\n", desc->iface_fns);
257 printf ("No Device Function Table.\n");
259 if (desc->operations && desc->operations->info)
260 desc->operations->info(desc);
262 ret_val = FPGA_SUCCESS;
264 printf ("%s: Invalid device descriptor\n", __FUNCTION__);
270 /* ------------------------------------------------------------------------- */
272 static int xilinx_validate(xilinx_desc *desc, char *fn)
277 if ((desc->family > min_xilinx_type) &&
278 (desc->family < max_xilinx_type)) {
279 if ((desc->iface > min_xilinx_iface_type) &&
280 (desc->iface < max_xilinx_iface_type)) {
284 printf ("%s: NULL part size\n", fn);
286 printf ("%s: Invalid Interface type, %d\n",
289 printf ("%s: Invalid family type, %d\n", fn, desc->family);
291 printf ("%s: NULL descriptor!\n", fn);