2 * (C) Copyright 2012-2013, Xilinx, Michal Simek
5 * Joe Hershberger <joe.hershberger@ni.com>
7 * SPDX-License-Identifier: GPL-2.0+
13 #include <asm/arch/hardware.h>
14 #include <asm/arch/sys_proto.h>
16 #define DEVCFG_CTRL_PCFG_PROG_B 0x40000000
17 #define DEVCFG_ISR_FATAL_ERROR_MASK 0x00740040
18 #define DEVCFG_ISR_ERROR_FLAGS_MASK 0x00340840
19 #define DEVCFG_ISR_RX_FIFO_OV 0x00040000
20 #define DEVCFG_ISR_DMA_DONE 0x00002000
21 #define DEVCFG_ISR_PCFG_DONE 0x00000004
22 #define DEVCFG_STATUS_DMA_CMD_Q_F 0x80000000
23 #define DEVCFG_STATUS_DMA_CMD_Q_E 0x40000000
24 #define DEVCFG_STATUS_DMA_DONE_CNT_MASK 0x30000000
25 #define DEVCFG_STATUS_PCFG_INIT 0x00000010
26 #define DEVCFG_MCTRL_RFIFO_FLUSH 0x00000002
27 #define DEVCFG_MCTRL_WFIFO_FLUSH 0x00000001
29 #ifndef CONFIG_SYS_FPGA_WAIT
30 #define CONFIG_SYS_FPGA_WAIT CONFIG_SYS_HZ/100 /* 10 ms */
33 #ifndef CONFIG_SYS_FPGA_PROG_TIME
34 #define CONFIG_SYS_FPGA_PROG_TIME CONFIG_SYS_HZ /* 1 s */
37 int zynq_info(Xilinx_desc *desc)
42 #define DUMMY_WORD 0xffffffff
44 /* Xilinx binary format header */
45 static const u32 bin_format[] = {
46 DUMMY_WORD, /* Dummy words */
54 0x000000bb, /* Sync word */
55 0x11220044, /* Sync word */
58 0xaa995566, /* Sync word */
65 * Load the whole word from unaligned buffer
66 * Keep in your mind that it is byte loading on little-endian system
68 static u32 load_word(const void *buf, u32 swap)
74 if (swap == SWAP_NO) {
75 for (p = 0; p < 4; p++) {
80 for (p = 3; p >= 0; p--) {
89 static u32 check_header(const void *buf)
93 u32 *test = (u32 *)buf;
95 debug("%s: Let's check bitstream header\n", __func__);
97 /* Checking that passing bin is not a bitstream */
98 for (i = 0; i < ARRAY_SIZE(bin_format); i++) {
99 pattern = load_word(&test[i], swap);
102 * Bitstreams in binary format are swapped
103 * compare to regular bistream.
104 * Do not swap dummy word but if swap is done assume
105 * that parsing buffer is binary format
107 if ((__swab32(pattern) != DUMMY_WORD) &&
108 (__swab32(pattern) == bin_format[i])) {
109 pattern = __swab32(pattern);
111 debug("%s: data swapped - let's swap\n", __func__);
114 debug("%s: %d/%x: pattern %x/%x bin_format\n", __func__, i,
115 (u32)&test[i], pattern, bin_format[i]);
116 if (pattern != bin_format[i]) {
117 debug("%s: Bitstream is not recognized\n", __func__);
121 debug("%s: Found bitstream header at %x %s swapinng\n", __func__,
122 (u32)buf, swap == SWAP_NO ? "without" : "with");
127 static void *check_data(u8 *buf, size_t bsize, u32 *swap)
129 u32 word, p = 0; /* possition */
131 /* Because buf doesn't need to be aligned let's read it by chars */
132 for (p = 0; p < bsize; p++) {
133 word = load_word(&buf[p], SWAP_NO);
134 debug("%s: word %x %x/%x\n", __func__, word, p, (u32)&buf[p]);
136 /* Find the first bitstream dummy word */
137 if (word == DUMMY_WORD) {
138 debug("%s: Found dummy word at position %x/%x\n",
139 __func__, p, (u32)&buf[p]);
140 *swap = check_header(&buf[p]);
142 /* FIXME add full bitstream checking here */
146 /* Loop can be huge - support CTRL + C */
154 int zynq_load(Xilinx_desc *desc, const void *buf, size_t bsize)
156 unsigned long ts; /* Timestamp */
158 u32 i, control, isr_status, status, swap, diff;
161 /* Detect if we are going working with partial or full bitstream */
162 if (bsize != desc->size) {
163 printf("%s: Working with partial bitstream\n", __func__);
167 buf_start = check_data((u8 *)buf, bsize, &swap);
171 /* Check if data is postpone from start */
172 diff = (u32)buf_start - (u32)buf;
174 printf("%s: Bitstream is not validated yet (diff %x)\n",
179 if ((u32)buf_start & 0x3) {
180 u32 *new_buf = (u32 *)((u32)buf & ~0x3);
182 printf("%s: Align buffer at %x to %x(swap %d)\n", __func__,
183 (u32)buf_start, (u32)new_buf, swap);
185 for (i = 0; i < (bsize/4); i++)
186 new_buf[i] = load_word(&buf_start[i], swap);
190 } else if (swap != SWAP_DONE) {
191 /* For bitstream which are aligned */
192 u32 *new_buf = (u32 *)buf;
194 printf("%s: Bitstream is not swapped(%d) - swap it\n", __func__,
197 for (i = 0; i < (bsize/4); i++)
198 new_buf[i] = load_word(&buf_start[i], swap);
204 zynq_slcr_devcfg_disable();
206 /* Setting PCFG_PROG_B signal to high */
207 control = readl(&devcfg_base->ctrl);
208 writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
209 /* Setting PCFG_PROG_B signal to low */
210 writel(control & ~DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
212 /* Polling the PCAP_INIT status for Reset */
214 while (readl(&devcfg_base->status) & DEVCFG_STATUS_PCFG_INIT) {
215 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
216 printf("%s: Timeout wait for INIT to clear\n",
222 /* Setting PCFG_PROG_B signal to high */
223 writel(control | DEVCFG_CTRL_PCFG_PROG_B, &devcfg_base->ctrl);
225 /* Polling the PCAP_INIT status for Set */
227 while (!(readl(&devcfg_base->status) &
228 DEVCFG_STATUS_PCFG_INIT)) {
229 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
230 printf("%s: Timeout wait for INIT to set\n",
237 isr_status = readl(&devcfg_base->int_sts);
239 /* Clear it all, so if Boot ROM comes back, it can proceed */
240 writel(0xFFFFFFFF, &devcfg_base->int_sts);
242 if (isr_status & DEVCFG_ISR_FATAL_ERROR_MASK) {
243 debug("%s: Fatal errors in PCAP 0x%X\n", __func__, isr_status);
245 /* If RX FIFO overflow, need to flush RX FIFO first */
246 if (isr_status & DEVCFG_ISR_RX_FIFO_OV) {
247 writel(DEVCFG_MCTRL_RFIFO_FLUSH, &devcfg_base->mctrl);
248 writel(0xFFFFFFFF, &devcfg_base->int_sts);
253 status = readl(&devcfg_base->status);
255 debug("%s: Status = 0x%08X\n", __func__, status);
257 if (status & DEVCFG_STATUS_DMA_CMD_Q_F) {
258 debug("%s: Error: device busy\n", __func__);
262 debug("%s: Device ready\n", __func__);
264 if (!(status & DEVCFG_STATUS_DMA_CMD_Q_E)) {
265 if (!(readl(&devcfg_base->int_sts) & DEVCFG_ISR_DMA_DONE)) {
266 /* Error state, transfer cannot occur */
267 debug("%s: ISR indicates error\n", __func__);
270 /* Clear out the status */
271 writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
275 if (status & DEVCFG_STATUS_DMA_DONE_CNT_MASK) {
276 /* Clear the count of completed DMA transfers */
277 writel(DEVCFG_STATUS_DMA_DONE_CNT_MASK, &devcfg_base->status);
280 debug("%s: Source = 0x%08X\n", __func__, (u32)buf);
281 debug("%s: Size = %zu\n", __func__, bsize);
283 /* Set up the transfer */
284 writel((u32)buf | 1, &devcfg_base->dma_src_addr);
285 writel(0xFFFFFFFF, &devcfg_base->dma_dst_addr);
286 writel(bsize >> 2, &devcfg_base->dma_src_len);
287 writel(0, &devcfg_base->dma_dst_len);
289 isr_status = readl(&devcfg_base->int_sts);
291 /* Polling the PCAP_INIT status for Set */
293 while (!(isr_status & DEVCFG_ISR_DMA_DONE)) {
294 if (isr_status & DEVCFG_ISR_ERROR_FLAGS_MASK) {
295 debug("%s: Error: isr = 0x%08X\n", __func__,
297 debug("%s: Write count = 0x%08X\n", __func__,
298 readl(&devcfg_base->write_count));
299 debug("%s: Read count = 0x%08X\n", __func__,
300 readl(&devcfg_base->read_count));
304 if (get_timer(ts) > CONFIG_SYS_FPGA_PROG_TIME) {
305 printf("%s: Timeout wait for DMA to complete\n",
309 isr_status = readl(&devcfg_base->int_sts);
312 debug("%s: DMA transfer is done\n", __func__);
314 /* Check FPGA configuration completion */
316 while (!(isr_status & DEVCFG_ISR_PCFG_DONE)) {
317 if (get_timer(ts) > CONFIG_SYS_FPGA_WAIT) {
318 printf("%s: Timeout wait for FPGA to config\n",
322 isr_status = readl(&devcfg_base->int_sts);
325 debug("%s: FPGA config done\n", __func__);
327 /* Clear out the DMA status */
328 writel(DEVCFG_ISR_DMA_DONE, &devcfg_base->int_sts);
331 zynq_slcr_devcfg_enable();
336 int zynq_dump(Xilinx_desc *desc, const void *buf, size_t bsize)