2 * Copyright 2006 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 #ifdef CONFIG_HARD_I2C
25 #include <i2c.h> /* Functional interface */
28 #include <asm/fsl_i2c.h> /* HW definitions */
30 #define I2C_TIMEOUT (CFG_HZ / 4)
32 /* Initialize the bus pointer to whatever one the SPD EEPROM is on.
33 * Default is bus 0. This is necessary because the DDR initialization
34 * runs from ROM, and we can't switch buses because we can't modify
35 * the global variables.
37 #ifdef CFG_SPD_BUS_NUM
38 static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = CFG_SPD_BUS_NUM;
40 static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0;
43 static volatile struct fsl_i2c *i2c_dev[2] = {
44 (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET),
45 #ifdef CFG_I2C2_OFFSET
46 (struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET)
51 i2c_init(int speed, int slaveadd)
53 volatile struct fsl_i2c *dev;
55 dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET);
57 writeb(0, &dev->cr); /* stop I2C controller */
58 writeb(0x3F, &dev->fdr); /* set bus speed */
59 writeb(0x3F, &dev->dfsrr); /* set default filter */
60 writeb(slaveadd, &dev->adr); /* write slave address */
61 writeb(0x0, &dev->sr); /* clear status register */
62 writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
64 #ifdef CFG_I2C2_OFFSET
65 dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET);
67 writeb(0, &dev->cr); /* stop I2C controller */
68 writeb(0x3F, &dev->fdr); /* set bus speed */
69 writeb(0x3F, &dev->dfsrr); /* set default filter */
70 writeb(slaveadd, &dev->adr); /* write slave address */
71 writeb(0x0, &dev->sr); /* clear status register */
72 writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
73 #endif /* CFG_I2C2_OFFSET */
79 ulong timeval = get_timer(0);
81 while (readb(&i2c_dev[i2c_bus_num]->sr) & I2C_SR_MBB) {
82 if (get_timer(timeval) > I2C_TIMEOUT) {
94 ulong timeval = get_timer(0);
97 csr = readb(&i2c_dev[i2c_bus_num]->sr);
98 if (!(csr & I2C_SR_MIF))
101 writeb(0x0, &i2c_dev[i2c_bus_num]->sr);
103 if (csr & I2C_SR_MAL) {
104 debug("i2c_wait: MAL\n");
108 if (!(csr & I2C_SR_MCF)) {
109 debug("i2c_wait: unfinished\n");
113 if (write == I2C_WRITE && (csr & I2C_SR_RXAK)) {
114 debug("i2c_wait: No RXACK\n");
119 } while (get_timer (timeval) < I2C_TIMEOUT);
121 debug("i2c_wait: timed out\n");
125 static __inline__ int
126 i2c_write_addr (u8 dev, u8 dir, int rsta)
128 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
129 | (rsta ? I2C_CR_RSTA : 0),
130 &i2c_dev[i2c_bus_num]->cr);
132 writeb((dev << 1) | dir, &i2c_dev[i2c_bus_num]->dr);
134 if (i2c_wait(I2C_WRITE) < 0)
140 static __inline__ int
141 __i2c_write(u8 *data, int length)
145 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
146 &i2c_dev[i2c_bus_num]->cr);
148 for (i = 0; i < length; i++) {
149 writeb(data[i], &i2c_dev[i2c_bus_num]->dr);
151 if (i2c_wait(I2C_WRITE) < 0)
158 static __inline__ int
159 __i2c_read(u8 *data, int length)
163 writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
164 &i2c_dev[i2c_bus_num]->cr);
167 readb(&i2c_dev[i2c_bus_num]->dr);
169 for (i = 0; i < length; i++) {
170 if (i2c_wait(I2C_READ) < 0)
173 /* Generate ack on last next to last byte */
175 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
176 &i2c_dev[i2c_bus_num]->cr);
178 /* Generate stop on last byte */
180 writeb(I2C_CR_MEN | I2C_CR_TXAK, &i2c_dev[i2c_bus_num]->cr);
182 data[i] = readb(&i2c_dev[i2c_bus_num]->dr);
189 i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
194 if (i2c_wait4bus() >= 0
195 && i2c_write_addr(dev, I2C_WRITE, 0) != 0
196 && __i2c_write(&a[4 - alen], alen) == alen
197 && i2c_write_addr(dev, I2C_READ, 1) != 0) {
198 i = __i2c_read(data, length);
201 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);
210 i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
215 if (i2c_wait4bus() >= 0
216 && i2c_write_addr(dev, I2C_WRITE, 0) != 0
217 && __i2c_write(&a[4 - alen], alen) == alen) {
218 i = __i2c_write(data, length);
221 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);
230 i2c_probe(uchar chip)
235 * Try to read the first location of the chip. The underlying
236 * driver doesn't appear to support sending just the chip address
237 * and looking for an <ACK> back.
241 return i2c_read(chip, 0, 1, (uchar *)&tmp, 1);
245 i2c_reg_read(uchar i2c_addr, uchar reg)
249 i2c_read(i2c_addr, reg, 1, buf, 1);
255 i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
257 i2c_write(i2c_addr, reg, 1, &val, 1);
260 int i2c_set_bus_num(unsigned int bus)
262 #ifdef CFG_I2C2_OFFSET
275 int i2c_set_bus_speed(unsigned int speed)
280 unsigned int i2c_get_bus_num(void)
285 unsigned int i2c_get_bus_speed(void)
289 #endif /* CONFIG_HARD_I2C */
290 #endif /* CONFIG_FSL_I2C */