2 * Copyright 2006 Freescale Semiconductor, Inc.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * Version 2 as published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 #ifdef CONFIG_HARD_I2C
25 #include <i2c.h> /* Functional interface */
28 #include <asm/fsl_i2c.h> /* HW definitions */
30 #define I2C_TIMEOUT (CFG_HZ / 4)
32 #define I2C_READ_BIT 1
33 #define I2C_WRITE_BIT 0
35 /* Initialize the bus pointer to whatever one the SPD EEPROM is on.
36 * Default is bus 0. This is necessary because the DDR initialization
37 * runs from ROM, and we can't switch buses because we can't modify
38 * the global variables.
40 #ifdef CFG_SPD_BUS_NUM
41 static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = CFG_SPD_BUS_NUM;
43 static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0;
46 static volatile struct fsl_i2c *i2c_dev[2] = {
47 (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET),
48 #ifdef CFG_I2C2_OFFSET
49 (struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET)
54 i2c_init(int speed, int slaveadd)
56 volatile struct fsl_i2c *dev;
58 dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET);
60 writeb(0, &dev->cr); /* stop I2C controller */
61 writeb(0x3F, &dev->fdr); /* set bus speed */
62 writeb(0x3F, &dev->dfsrr); /* set default filter */
63 writeb(slaveadd << 1, &dev->adr); /* write slave address */
64 writeb(0x0, &dev->sr); /* clear status register */
65 writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
67 #ifdef CFG_I2C2_OFFSET
68 dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET);
70 writeb(0, &dev->cr); /* stop I2C controller */
71 writeb(0x3F, &dev->fdr); /* set bus speed */
72 writeb(0x3F, &dev->dfsrr); /* set default filter */
73 writeb(slaveadd, &dev->adr); /* write slave address */
74 writeb(0x0, &dev->sr); /* clear status register */
75 writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */
76 #endif /* CFG_I2C2_OFFSET */
82 ulong timeval = get_timer(0);
84 while (readb(&i2c_dev[i2c_bus_num]->sr) & I2C_SR_MBB) {
85 if (get_timer(timeval) > I2C_TIMEOUT) {
97 ulong timeval = get_timer(0);
100 csr = readb(&i2c_dev[i2c_bus_num]->sr);
101 if (!(csr & I2C_SR_MIF))
104 writeb(0x0, &i2c_dev[i2c_bus_num]->sr);
106 if (csr & I2C_SR_MAL) {
107 debug("i2c_wait: MAL\n");
111 if (!(csr & I2C_SR_MCF)) {
112 debug("i2c_wait: unfinished\n");
116 if (write == I2C_WRITE_BIT && (csr & I2C_SR_RXAK)) {
117 debug("i2c_wait: No RXACK\n");
122 } while (get_timer (timeval) < I2C_TIMEOUT);
124 debug("i2c_wait: timed out\n");
128 static __inline__ int
129 i2c_write_addr (u8 dev, u8 dir, int rsta)
131 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX
132 | (rsta ? I2C_CR_RSTA : 0),
133 &i2c_dev[i2c_bus_num]->cr);
135 writeb((dev << 1) | dir, &i2c_dev[i2c_bus_num]->dr);
137 if (i2c_wait(I2C_WRITE_BIT) < 0)
143 static __inline__ int
144 __i2c_write(u8 *data, int length)
148 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_MTX,
149 &i2c_dev[i2c_bus_num]->cr);
151 for (i = 0; i < length; i++) {
152 writeb(data[i], &i2c_dev[i2c_bus_num]->dr);
154 if (i2c_wait(I2C_WRITE_BIT) < 0)
161 static __inline__ int
162 __i2c_read(u8 *data, int length)
166 writeb(I2C_CR_MEN | I2C_CR_MSTA | ((length == 1) ? I2C_CR_TXAK : 0),
167 &i2c_dev[i2c_bus_num]->cr);
170 readb(&i2c_dev[i2c_bus_num]->dr);
172 for (i = 0; i < length; i++) {
173 if (i2c_wait(I2C_READ_BIT) < 0)
176 /* Generate ack on last next to last byte */
178 writeb(I2C_CR_MEN | I2C_CR_MSTA | I2C_CR_TXAK,
179 &i2c_dev[i2c_bus_num]->cr);
181 /* Generate stop on last byte */
183 writeb(I2C_CR_MEN | I2C_CR_TXAK, &i2c_dev[i2c_bus_num]->cr);
185 data[i] = readb(&i2c_dev[i2c_bus_num]->dr);
192 i2c_read(u8 dev, uint addr, int alen, u8 *data, int length)
197 if (i2c_wait4bus() >= 0
198 && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
199 && __i2c_write(&a[4 - alen], alen) == alen
200 && i2c_write_addr(dev, I2C_READ_BIT, 1) != 0) {
201 i = __i2c_read(data, length);
204 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);
213 i2c_write(u8 dev, uint addr, int alen, u8 *data, int length)
218 if (i2c_wait4bus() >= 0
219 && i2c_write_addr(dev, I2C_WRITE_BIT, 0) != 0
220 && __i2c_write(&a[4 - alen], alen) == alen) {
221 i = __i2c_write(data, length);
224 writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr);
233 i2c_probe(uchar chip)
238 * Try to read the first location of the chip. The underlying
239 * driver doesn't appear to support sending just the chip address
240 * and looking for an <ACK> back.
244 return i2c_read(chip, 0, 1, (uchar *)&tmp, 1);
248 i2c_reg_read(uchar i2c_addr, uchar reg)
252 i2c_read(i2c_addr, reg, 1, buf, 1);
258 i2c_reg_write(uchar i2c_addr, uchar reg, uchar val)
260 i2c_write(i2c_addr, reg, 1, &val, 1);
263 int i2c_set_bus_num(unsigned int bus)
265 #ifdef CFG_I2C2_OFFSET
278 int i2c_set_bus_speed(unsigned int speed)
283 unsigned int i2c_get_bus_num(void)
288 unsigned int i2c_get_bus_speed(void)
292 #endif /* CONFIG_HARD_I2C */
293 #endif /* CONFIG_FSL_I2C */