git.sur5r.net Git - u-boot/blob - drivers/fsl_pci_init.c

   1 /*
   2  * Copyright 2007 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License
  14  * along with this program; if not, write to the Free Software
  15  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  16  * MA 02111-1307 USA
  17  */
  18
  19 #include <common.h>
  20
  21 #ifdef CONFIG_FSL_PCI_INIT
  22
  23 /*
  24  * PCI/PCIE Controller initialization for mpc85xx/mpc86xx soc's
  25  *
  26  * Initialize controller and call the common driver/pci pci_hose_scan to
  27  * scan for bridges and devices.
  28  *
  29  * Hose fields which need to be pre-initialized by board specific code:
  30  *   regions[]
  31  *   first_busno
  32  *
  33  * Fields updated:
  34  *   last_busno
  35  */
  36
  37 #include <pci.h>
  38 #include <asm/immap_fsl_pci.h>
  39
  40 void pciauto_prescan_setup_bridge(struct pci_controller *hose,
  41                                 pci_dev_t dev, int sub_bus);
  42 void pciauto_postscan_setup_bridge(struct pci_controller *hose,
  43                                 pci_dev_t dev, int sub_bus);
  44
  45 void pciauto_config_init(struct pci_controller *hose);
  46 void
  47 fsl_pci_init(struct pci_controller *hose)
  48 {
  49         u16 temp16;
  50         u32 temp32;
  51         int busno = hose->first_busno;
  52         int enabled;
  53         u16 ltssm;
  54         u8 temp8;
  55         int r;
  56         int bridge;
  57         unsigned long bus_lower_temp;
  58         volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) hose->cfg_addr;
  59         pci_dev_t dev = PCI_BDF(busno,0,0);
  60
  61         /* Initialize ATMU registers based on hose regions and flags */
  62         volatile pot_t *po=&pci->pot[1];        /* skip 0 */
  63         volatile pit_t *pi=&pci->pit[0];        /* ranges from: 3 to 1 */
  64
  65 #ifdef DEBUG
  66         int neg_link_w;
  67 #endif
  68
  69         for (r=0; r<hose->region_count; r++) {
  70                 if (hose->regions[r].flags & PCI_REGION_MEMORY) { /* inbound */
  71                         pi->pitar = (hose->regions[r].bus_start >> 12) & 0x000fffff;
  72                         pi->piwbar = (hose->regions[r].phys_start >> 12) & 0x000fffff;
  73                         pi->piwbear = 0;
  74                         pi->piwar = PIWAR_EN | PIWAR_PF | PIWAR_LOCAL |
  75                                 PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP |
  76                                 (__ilog2(hose->regions[r].size) - 1);
  77                         pi++;
  78                 } else { /* Outbound */
  79                         po->powbar = (hose->regions[r].phys_start >> 12) & 0x000fffff;
  80                         po->potar = (hose->regions[r].bus_start >> 12) & 0x000fffff;
  81                         po->potear = 0;
  82                         if (hose->regions[r].flags & PCI_REGION_IO)
  83                                 po->powar = POWAR_EN | POWAR_IO_READ | POWAR_IO_WRITE |
  84                                         (__ilog2(hose->regions[r].size) - 1);
  85                         else
  86                                 po->powar = POWAR_EN | POWAR_MEM_READ | POWAR_MEM_WRITE |
  87                                         (__ilog2(hose->regions[r].size) - 1);
  88                         po++;
  89                 }
  90         }
  91
  92         pci_register_hose(hose);
  93         pciauto_config_init(hose);      /* grab pci_{mem,prefetch,io} */
  94         hose->current_busno = hose->first_busno;
  95
  96         pci->pedr = 0xffffffff;         /* Clear any errors */
  97         pci->peer = ~0x20140;           /* Enable All Error Interupts except
  98                                          * - Master abort (pci)
  99                                          * - Master PERR (pci)
 100                                          * - ICCA (PCIe)
 101                                          */
 102         pci_hose_read_config_dword (hose, dev, PCI_DCR, &temp32);
 103         temp32 |= 0xf000e;              /* set URR, FER, NFER (but not CER) */
 104         pci_hose_write_config_dword(hose, dev, PCI_DCR, temp32);
 105
 106         pci_hose_read_config_byte (hose, dev, PCI_HEADER_TYPE, &temp8);
 107         bridge = temp8 & PCI_HEADER_TYPE_BRIDGE; /* Bridge, such as pcie */
 108
 109         if ( bridge ) {
 110
 111                 pci_hose_read_config_word(hose, dev, PCI_LTSSM, &ltssm);
 112                 enabled = ltssm >= PCI_LTSSM_L0;
 113
 114                 if (!enabled) {
 115                         debug("....PCIE link error.  Skipping scan."
 116                               "LTSSM=0x%02x\n", ltssm);
 117                         hose->last_busno = hose->first_busno;
 118                         return;
 119                 }
 120
 121                 pci->pme_msg_det = 0xffffffff;
 122                 pci->pme_msg_int_en = 0xffffffff;
 123 #ifdef DEBUG
 124                 pci_hose_read_config_word(hose, dev, PCI_LSR, &temp16);
 125                 neg_link_w = (temp16 & 0x3f0 ) >> 4;
 126                 printf("...PCIE LTSSM=0x%x, Negotiated link width=%d\n",
 127                       ltssm, neg_link_w);
 128 #endif
 129                 hose->current_busno++; /* Start scan with secondary */
 130                 pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
 131
 132         }
 133
 134         /* Use generic setup_device to initialize standard pci regs,
 135          * but do not allocate any windows since any BAR found (such
 136          * as PCSRBAR) is not in this cpu's memory space.
 137          */
 138         bus_lower_temp = hose->pci_mem->bus_lower;
 139         pciauto_setup_device(hose, dev, 0, hose->pci_mem,
 140                              hose->pci_prefetch, hose->pci_io);
 141         hose->pci_mem->bus_lower = bus_lower_temp;
 142
 143 #ifndef CONFIG_PCI_NOSCAN
 144         printf ("               Scanning PCI bus %02x\n", hose->current_busno);
 145         hose->last_busno = pci_hose_scan_bus(hose,hose->current_busno);
 146
 147         if ( bridge ) { /* update limit regs and subordinate busno */
 148                 pciauto_postscan_setup_bridge(hose, dev, hose->last_busno);
 149         }
 150 #else
 151         hose->last_busno = hose->current_busno;
 152 #endif
 153
 154         /* Clear all error indications */
 155
 156         pci->pme_msg_det = 0xffffffff;
 157         pci->pedr = 0xffffffff;
 158
 159         pci_hose_read_config_word (hose, dev, PCI_DSR, &temp16);
 160         if (temp16) {
 161                 pci_hose_write_config_word(hose, dev,
 162                                         PCI_DSR, 0xffff);
 163         }
 164
 165         pci_hose_read_config_word (hose, dev, PCI_SEC_STATUS, &temp16);
 166         if (temp16) {
 167                 pci_hose_write_config_word(hose, dev, PCI_SEC_STATUS, 0xffff);
 168         }
 169 }
 170
 171 #endif /* CONFIG_FSL_PCI */