2 * Memory Setup stuff - taken from blob memsetup.S
4 * Copyright (C) 2009 Jens Scharsig (js_at_ng@scharsoft.de)
6 * Copyright (C) 2005 HP Labs
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 * As the code is right now, it expects all PIO ports A,B,C,...
31 * to be evenly spaced in the memory map:
32 * ATMEL_BASE_PIOA + port * sizeof at91pio_t
33 * This might not necessaryly be true in future Atmel SoCs.
34 * This code should be fixed to use a pointer array to the ports.
40 #include <asm/sizes.h>
41 #include <asm/arch/hardware.h>
42 #include <asm/arch/at91_pio.h>
44 int at91_set_pio_pullup(unsigned port, unsigned pin, int use_pullup)
46 at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
49 if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
52 writel(1 << pin, &pio->port[port].puer);
54 writel(1 << pin, &pio->port[port].pudr);
55 writel(mask, &pio->port[port].per);
61 * mux the pin to the "GPIO" peripheral role.
63 int at91_set_pio_periph(unsigned port, unsigned pin, int use_pullup)
65 at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
68 if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
70 writel(mask, &pio->port[port].idr);
71 at91_set_pio_pullup(port, pin, use_pullup);
72 writel(mask, &pio->port[port].per);
78 * mux the pin to the "A" internal peripheral role.
80 int at91_set_a_periph(unsigned port, unsigned pin, int use_pullup)
82 at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
85 if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
87 writel(mask, &pio->port[port].idr);
88 at91_set_pio_pullup(port, pin, use_pullup);
89 #if defined(CPU_HAS_PIO3)
90 writel(readl(&pio->port[port].abcdsr1) & ~mask,
91 &pio->port[port].abcdsr1);
92 writel(readl(&pio->port[port].abcdsr2) & ~mask,
93 &pio->port[port].abcdsr2);
95 writel(mask, &pio->port[port].asr);
97 writel(mask, &pio->port[port].pdr);
103 * mux the pin to the "B" internal peripheral role.
105 int at91_set_b_periph(unsigned port, unsigned pin, int use_pullup)
107 at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
110 if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
112 writel(mask, &pio->port[port].idr);
113 at91_set_pio_pullup(port, pin, use_pullup);
114 #if defined(CPU_HAS_PIO3)
115 writel(readl(&pio->port[port].abcdsr1) | mask,
116 &pio->port[port].abcdsr1);
117 writel(readl(&pio->port[port].abcdsr2) & ~mask,
118 &pio->port[port].abcdsr2);
120 writel(mask, &pio->port[port].bsr);
122 writel(mask, &pio->port[port].pdr);
127 #if defined(CPU_HAS_PIO3)
129 * mux the pin to the "C" internal peripheral role.
131 int at91_set_c_periph(unsigned port, unsigned pin, int use_pullup)
133 at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
136 if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
138 writel(mask, &pio->port[port].idr);
139 at91_set_pio_pullup(port, pin, use_pullup);
140 writel(readl(&pio->port[port].abcdsr1) & ~mask,
141 &pio->port[port].abcdsr1);
142 writel(readl(&pio->port[port].abcdsr2) | mask,
143 &pio->port[port].abcdsr2);
144 writel(mask, &pio->port[port].pdr);
150 * mux the pin to the "D" internal peripheral role.
152 int at91_set_d_periph(unsigned port, unsigned pin, int use_pullup)
154 at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
157 if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
159 writel(mask, &pio->port[port].idr);
160 at91_set_pio_pullup(port, pin, use_pullup);
161 writel(readl(&pio->port[port].abcdsr1) | mask,
162 &pio->port[port].abcdsr1);
163 writel(readl(&pio->port[port].abcdsr2) | mask,
164 &pio->port[port].abcdsr2);
165 writel(mask, &pio->port[port].pdr);
172 * mux the pin to the gpio controller (instead of "A" or "B" peripheral), and
173 * configure it for an input.
175 int at91_set_pio_input(unsigned port, u32 pin, int use_pullup)
177 at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
180 if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
182 writel(mask, &pio->port[port].idr);
183 at91_set_pio_pullup(port, pin, use_pullup);
184 writel(mask, &pio->port[port].odr);
185 writel(mask, &pio->port[port].per);
191 * mux the pin to the gpio controller (instead of "A" or "B" peripheral),
192 * and configure it for an output.
194 int at91_set_pio_output(unsigned port, u32 pin, int value)
196 at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
199 if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
201 writel(mask, &pio->port[port].idr);
202 writel(mask, &pio->port[port].pudr);
204 writel(mask, &pio->port[port].sodr);
206 writel(mask, &pio->port[port].codr);
207 writel(mask, &pio->port[port].oer);
208 writel(mask, &pio->port[port].per);
214 * enable/disable the glitch filter. mostly used with IRQ handling.
216 int at91_set_pio_deglitch(unsigned port, unsigned pin, int is_on)
218 at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
221 if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
224 #if defined(CPU_HAS_PIO3)
225 writel(mask, &pio->port[port].ifscdr);
227 writel(mask, &pio->port[port].ifer);
229 writel(mask, &pio->port[port].ifdr);
235 #if defined(CPU_HAS_PIO3)
237 * enable/disable the debounce filter.
239 int at91_set_pio_debounce(unsigned port, unsigned pin, int is_on, int div)
241 at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
244 if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
247 writel(mask, &pio->port[port].ifscer);
248 writel(div & PIO_SCDR_DIV, &pio->port[port].scdr);
249 writel(mask, &pio->port[port].ifer);
251 writel(mask, &pio->port[port].ifdr);
258 * enable/disable the pull-down.
259 * If pull-up already enabled while calling the function, we disable it.
261 int at91_set_pio_pulldown(unsigned port, unsigned pin, int is_on)
263 at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
266 if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
268 writel(mask, &pio->port[port].pudr);
270 writel(mask, &pio->port[port].ppder);
272 writel(mask, &pio->port[port].ppddr);
278 * disable Schmitt trigger
280 int at91_set_pio_disable_schmitt_trig(unsigned port, unsigned pin)
282 at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
285 if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
287 writel(readl(&pio->port[port].schmitt) | mask,
288 &pio->port[port].schmitt);
295 * enable/disable the multi-driver. This is only valid for output and
296 * allows the output pin to run as an open collector output.
298 int at91_set_pio_multi_drive(unsigned port, unsigned pin, int is_on)
300 at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
303 if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
306 writel(mask, &pio->port[port].mder);
308 writel(mask, &pio->port[port].mddr);
314 * assuming the pin is muxed as a gpio output, set its value.
316 int at91_set_pio_value(unsigned port, unsigned pin, int value)
318 at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
321 if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
324 writel(mask, &pio->port[port].sodr);
326 writel(mask, &pio->port[port].codr);
332 * read the pin's value (works even if it's not muxed as a gpio).
334 int at91_get_pio_value(unsigned port, unsigned pin)
337 at91_pio_t *pio = (at91_pio_t *) ATMEL_BASE_PIOA;
340 if ((port < ATMEL_PIO_PORTS) && (pin < 32)) {
342 pdsr = readl(&pio->port[port].pdsr) & mask;