2 * Atmel PIO4 device driver
4 * Copyright (C) 2015 Atmel Corporation
5 * Wenyou.Yang <wenyou.yang@atmel.com>
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/hardware.h>
12 #include <mach/gpio.h>
13 #include <mach/atmel_pio4.h>
15 #define ATMEL_PIO4_PINS_PER_BANK 32
18 * Register Field Definitions
20 #define ATMEL_PIO4_CFGR_FUNC (0x7 << 0)
21 #define ATMEL_PIO4_CFGR_FUNC_GPIO (0x0 << 0)
22 #define ATMEL_PIO4_CFGR_FUNC_PERIPH_A (0x1 << 0)
23 #define ATMEL_PIO4_CFGR_FUNC_PERIPH_B (0x2 << 0)
24 #define ATMEL_PIO4_CFGR_FUNC_PERIPH_C (0x3 << 0)
25 #define ATMEL_PIO4_CFGR_FUNC_PERIPH_D (0x4 << 0)
26 #define ATMEL_PIO4_CFGR_FUNC_PERIPH_E (0x5 << 0)
27 #define ATMEL_PIO4_CFGR_FUNC_PERIPH_F (0x6 << 0)
28 #define ATMEL_PIO4_CFGR_FUNC_PERIPH_G (0x7 << 0)
29 #define ATMEL_PIO4_CFGR_DIR (0x1 << 8)
30 #define ATMEL_PIO4_CFGR_PUEN (0x1 << 9)
31 #define ATMEL_PIO4_CFGR_PDEN (0x1 << 10)
32 #define ATMEL_PIO4_CFGR_IFEN (0x1 << 12)
33 #define ATMEL_PIO4_CFGR_IFSCEN (0x1 << 13)
34 #define ATMEL_PIO4_CFGR_OPD (0x1 << 14)
35 #define ATMEL_PIO4_CFGR_SCHMITT (0x1 << 15)
36 #define ATMEL_PIO4_CFGR_DRVSTR (0x3 << 16)
37 #define ATMEL_PIO4_CFGR_DRVSTR_LOW0 (0x0 << 16)
38 #define ATMEL_PIO4_CFGR_DRVSTR_LOW1 (0x1 << 16)
39 #define ATMEL_PIO4_CFGR_DRVSTR_MEDIUM (0x2 << 16)
40 #define ATMEL_PIO4_CFGR_DRVSTR_HIGH (0x3 << 16)
41 #define ATMEL_PIO4_CFGR_EVTSEL (0x7 << 24)
42 #define ATMEL_PIO4_CFGR_EVTSEL_FALLING (0x0 << 24)
43 #define ATMEL_PIO4_CFGR_EVTSEL_RISING (0x1 << 24)
44 #define ATMEL_PIO4_CFGR_EVTSEL_BOTH (0x2 << 24)
45 #define ATMEL_PIO4_CFGR_EVTSEL_LOW (0x3 << 24)
46 #define ATMEL_PIO4_CFGR_EVTSEL_HIGH (0x4 << 24)
47 #define ATMEL_PIO4_CFGR_PCFS (0x1 << 29)
48 #define ATMEL_PIO4_CFGR_ICFS (0x1 << 30)
50 static struct atmel_pio4_port *atmel_pio4_port_base(u32 port)
52 struct atmel_pio4_port *base = NULL;
56 base = (struct atmel_pio4_port *)ATMEL_BASE_PIOA;
59 base = (struct atmel_pio4_port *)ATMEL_BASE_PIOB;
62 base = (struct atmel_pio4_port *)ATMEL_BASE_PIOC;
65 base = (struct atmel_pio4_port *)ATMEL_BASE_PIOD;
68 printf("Error: Atmel PIO4: Failed to get PIO base of port#%d!\n",
76 static int atmel_pio4_config_io_func(u32 port, u32 pin,
77 u32 func, u32 use_pullup)
79 struct atmel_pio4_port *port_base;
82 if (pin >= ATMEL_PIO4_PINS_PER_BANK)
85 port_base = atmel_pio4_port_base(port);
91 reg |= use_pullup ? ATMEL_PIO4_CFGR_PUEN : 0;
93 writel(mask, &port_base->mskr);
94 writel(reg, &port_base->cfgr);
99 int atmel_pio4_set_gpio(u32 port, u32 pin, u32 use_pullup)
101 return atmel_pio4_config_io_func(port, pin,
102 ATMEL_PIO4_CFGR_FUNC_GPIO,
106 int atmel_pio4_set_a_periph(u32 port, u32 pin, u32 use_pullup)
108 return atmel_pio4_config_io_func(port, pin,
109 ATMEL_PIO4_CFGR_FUNC_PERIPH_A,
113 int atmel_pio4_set_b_periph(u32 port, u32 pin, u32 use_pullup)
115 return atmel_pio4_config_io_func(port, pin,
116 ATMEL_PIO4_CFGR_FUNC_PERIPH_B,
120 int atmel_pio4_set_c_periph(u32 port, u32 pin, u32 use_pullup)
122 return atmel_pio4_config_io_func(port, pin,
123 ATMEL_PIO4_CFGR_FUNC_PERIPH_C,
127 int atmel_pio4_set_d_periph(u32 port, u32 pin, u32 use_pullup)
129 return atmel_pio4_config_io_func(port, pin,
130 ATMEL_PIO4_CFGR_FUNC_PERIPH_D,
134 int atmel_pio4_set_e_periph(u32 port, u32 pin, u32 use_pullup)
136 return atmel_pio4_config_io_func(port, pin,
137 ATMEL_PIO4_CFGR_FUNC_PERIPH_E,
141 int atmel_pio4_set_f_periph(u32 port, u32 pin, u32 use_pullup)
143 return atmel_pio4_config_io_func(port, pin,
144 ATMEL_PIO4_CFGR_FUNC_PERIPH_F,
148 int atmel_pio4_set_g_periph(u32 port, u32 pin, u32 use_pullup)
150 return atmel_pio4_config_io_func(port, pin,
151 ATMEL_PIO4_CFGR_FUNC_PERIPH_G,
155 int atmel_pio4_set_pio_output(u32 port, u32 pin, u32 value)
157 struct atmel_pio4_port *port_base;
160 if (pin >= ATMEL_PIO4_PINS_PER_BANK)
163 port_base = atmel_pio4_port_base(port);
168 reg = ATMEL_PIO4_CFGR_FUNC_GPIO | ATMEL_PIO4_CFGR_DIR;
170 writel(mask, &port_base->mskr);
171 writel(reg, &port_base->cfgr);
174 writel(mask, &port_base->sodr);
176 writel(mask, &port_base->codr);
181 int atmel_pio4_get_pio_input(u32 port, u32 pin)
183 struct atmel_pio4_port *port_base;
186 if (pin >= ATMEL_PIO4_PINS_PER_BANK)
189 port_base = atmel_pio4_port_base(port);
194 reg = ATMEL_PIO4_CFGR_FUNC_GPIO;
196 writel(mask, &port_base->mskr);
197 writel(reg, &port_base->cfgr);
199 return (readl(&port_base->pdsr) & mask) ? 1 : 0;
202 #ifdef CONFIG_DM_GPIO
203 static int atmel_pio4_direction_input(struct udevice *dev, unsigned offset)
205 struct at91_port_platdata *plat = dev_get_platdata(dev);
206 struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr;
207 u32 mask = 0x01 << offset;
208 u32 reg = ATMEL_PIO4_CFGR_FUNC_GPIO;
210 writel(mask, &port_base->mskr);
211 writel(reg, &port_base->cfgr);
216 static int atmel_pio4_direction_output(struct udevice *dev,
217 unsigned offset, int value)
219 struct at91_port_platdata *plat = dev_get_platdata(dev);
220 struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr;
221 u32 mask = 0x01 << offset;
222 u32 reg = ATMEL_PIO4_CFGR_FUNC_GPIO | ATMEL_PIO4_CFGR_DIR;
224 writel(mask, &port_base->mskr);
225 writel(reg, &port_base->cfgr);
228 writel(mask, &port_base->sodr);
230 writel(mask, &port_base->codr);
235 static int atmel_pio4_get_value(struct udevice *dev, unsigned offset)
237 struct at91_port_platdata *plat = dev_get_platdata(dev);
238 struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr;
239 u32 mask = 0x01 << offset;
241 return (readl(&port_base->pdsr) & mask) ? 1 : 0;
244 static int atmel_pio4_set_value(struct udevice *dev,
245 unsigned offset, int value)
247 struct at91_port_platdata *plat = dev_get_platdata(dev);
248 struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr;
249 u32 mask = 0x01 << offset;
252 writel(mask, &port_base->sodr);
254 writel(mask, &port_base->codr);
259 static int atmel_pio4_get_function(struct udevice *dev, unsigned offset)
261 struct at91_port_platdata *plat = dev_get_platdata(dev);
262 struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr;
263 u32 mask = 0x01 << offset;
265 writel(mask, &port_base->mskr);
267 return (readl(&port_base->cfgr) &
268 ATMEL_PIO4_CFGR_DIR) ? GPIOF_OUTPUT : GPIOF_INPUT;
271 static const struct dm_gpio_ops atmel_pio4_ops = {
272 .direction_input = atmel_pio4_direction_input,
273 .direction_output = atmel_pio4_direction_output,
274 .get_value = atmel_pio4_get_value,
275 .set_value = atmel_pio4_set_value,
276 .get_function = atmel_pio4_get_function,
279 static int atmel_pio4_probe(struct udevice *dev)
281 struct at91_port_platdata *plat = dev_get_platdata(dev);
282 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
284 uc_priv->bank_name = plat->bank_name;
285 uc_priv->gpio_count = ATMEL_PIO4_PINS_PER_BANK;
290 U_BOOT_DRIVER(gpio_atmel_pio4) = {
291 .name = "gpio_atmel_pio4",
293 .ops = &atmel_pio4_ops,
294 .probe = atmel_pio4_probe,