2 * Atmel PIO4 device driver
4 * Copyright (C) 2015 Atmel Corporation
5 * Wenyou.Yang <wenyou.yang@atmel.com>
7 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/arch/hardware.h>
12 #include <mach/gpio.h>
13 #include <mach/atmel_pio4.h>
15 static struct atmel_pio4_port *atmel_pio4_port_base(u32 port)
17 struct atmel_pio4_port *base = NULL;
21 base = (struct atmel_pio4_port *)ATMEL_BASE_PIOA;
24 base = (struct atmel_pio4_port *)ATMEL_BASE_PIOB;
27 base = (struct atmel_pio4_port *)ATMEL_BASE_PIOC;
30 base = (struct atmel_pio4_port *)ATMEL_BASE_PIOD;
33 printf("Error: Atmel PIO4: Failed to get PIO base of port#%d!\n",
41 static int atmel_pio4_config_io_func(u32 port, u32 pin,
42 u32 func, u32 use_pullup)
44 struct atmel_pio4_port *port_base;
47 if (pin >= ATMEL_PIO_NPINS_PER_BANK)
50 port_base = atmel_pio4_port_base(port);
56 reg |= use_pullup ? ATMEL_PIO_PUEN_MASK : 0;
58 writel(mask, &port_base->mskr);
59 writel(reg, &port_base->cfgr);
64 int atmel_pio4_set_gpio(u32 port, u32 pin, u32 use_pullup)
66 return atmel_pio4_config_io_func(port, pin,
67 ATMEL_PIO_CFGR_FUNC_GPIO,
71 int atmel_pio4_set_a_periph(u32 port, u32 pin, u32 use_pullup)
73 return atmel_pio4_config_io_func(port, pin,
74 ATMEL_PIO_CFGR_FUNC_PERIPH_A,
78 int atmel_pio4_set_b_periph(u32 port, u32 pin, u32 use_pullup)
80 return atmel_pio4_config_io_func(port, pin,
81 ATMEL_PIO_CFGR_FUNC_PERIPH_B,
85 int atmel_pio4_set_c_periph(u32 port, u32 pin, u32 use_pullup)
87 return atmel_pio4_config_io_func(port, pin,
88 ATMEL_PIO_CFGR_FUNC_PERIPH_C,
92 int atmel_pio4_set_d_periph(u32 port, u32 pin, u32 use_pullup)
94 return atmel_pio4_config_io_func(port, pin,
95 ATMEL_PIO_CFGR_FUNC_PERIPH_D,
99 int atmel_pio4_set_e_periph(u32 port, u32 pin, u32 use_pullup)
101 return atmel_pio4_config_io_func(port, pin,
102 ATMEL_PIO_CFGR_FUNC_PERIPH_E,
106 int atmel_pio4_set_f_periph(u32 port, u32 pin, u32 use_pullup)
108 return atmel_pio4_config_io_func(port, pin,
109 ATMEL_PIO_CFGR_FUNC_PERIPH_F,
113 int atmel_pio4_set_g_periph(u32 port, u32 pin, u32 use_pullup)
115 return atmel_pio4_config_io_func(port, pin,
116 ATMEL_PIO_CFGR_FUNC_PERIPH_G,
120 int atmel_pio4_set_pio_output(u32 port, u32 pin, u32 value)
122 struct atmel_pio4_port *port_base;
125 if (pin >= ATMEL_PIO_NPINS_PER_BANK)
128 port_base = atmel_pio4_port_base(port);
133 reg = ATMEL_PIO_CFGR_FUNC_GPIO | ATMEL_PIO_DIR_MASK;
135 writel(mask, &port_base->mskr);
136 writel(reg, &port_base->cfgr);
139 writel(mask, &port_base->sodr);
141 writel(mask, &port_base->codr);
146 int atmel_pio4_get_pio_input(u32 port, u32 pin)
148 struct atmel_pio4_port *port_base;
151 if (pin >= ATMEL_PIO_NPINS_PER_BANK)
154 port_base = atmel_pio4_port_base(port);
159 reg = ATMEL_PIO_CFGR_FUNC_GPIO;
161 writel(mask, &port_base->mskr);
162 writel(reg, &port_base->cfgr);
164 return (readl(&port_base->pdsr) & mask) ? 1 : 0;
167 #ifdef CONFIG_DM_GPIO
168 static int atmel_pio4_direction_input(struct udevice *dev, unsigned offset)
170 struct at91_port_platdata *plat = dev_get_platdata(dev);
171 struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr;
172 u32 mask = 0x01 << offset;
173 u32 reg = ATMEL_PIO_CFGR_FUNC_GPIO;
175 writel(mask, &port_base->mskr);
176 writel(reg, &port_base->cfgr);
181 static int atmel_pio4_direction_output(struct udevice *dev,
182 unsigned offset, int value)
184 struct at91_port_platdata *plat = dev_get_platdata(dev);
185 struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr;
186 u32 mask = 0x01 << offset;
187 u32 reg = ATMEL_PIO_CFGR_FUNC_GPIO | ATMEL_PIO_DIR_MASK;
189 writel(mask, &port_base->mskr);
190 writel(reg, &port_base->cfgr);
193 writel(mask, &port_base->sodr);
195 writel(mask, &port_base->codr);
200 static int atmel_pio4_get_value(struct udevice *dev, unsigned offset)
202 struct at91_port_platdata *plat = dev_get_platdata(dev);
203 struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr;
204 u32 mask = 0x01 << offset;
206 return (readl(&port_base->pdsr) & mask) ? 1 : 0;
209 static int atmel_pio4_set_value(struct udevice *dev,
210 unsigned offset, int value)
212 struct at91_port_platdata *plat = dev_get_platdata(dev);
213 struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr;
214 u32 mask = 0x01 << offset;
217 writel(mask, &port_base->sodr);
219 writel(mask, &port_base->codr);
224 static int atmel_pio4_get_function(struct udevice *dev, unsigned offset)
226 struct at91_port_platdata *plat = dev_get_platdata(dev);
227 struct atmel_pio4_port *port_base = (atmel_pio4_port *)plat->base_addr;
228 u32 mask = 0x01 << offset;
230 writel(mask, &port_base->mskr);
232 return (readl(&port_base->cfgr) &
233 ATMEL_PIO_DIR_MASK) ? GPIOF_OUTPUT : GPIOF_INPUT;
236 static const struct dm_gpio_ops atmel_pio4_ops = {
237 .direction_input = atmel_pio4_direction_input,
238 .direction_output = atmel_pio4_direction_output,
239 .get_value = atmel_pio4_get_value,
240 .set_value = atmel_pio4_set_value,
241 .get_function = atmel_pio4_get_function,
244 static int atmel_pio4_probe(struct udevice *dev)
246 struct at91_port_platdata *plat = dev_get_platdata(dev);
247 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
249 uc_priv->bank_name = plat->bank_name;
250 uc_priv->gpio_count = ATMEL_PIO_NPINS_PER_BANK;
255 U_BOOT_DRIVER(gpio_atmel_pio4) = {
256 .name = "gpio_atmel_pio4",
258 .ops = &atmel_pio4_ops,
259 .probe = atmel_pio4_probe,