2 * Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <linux/bitops.h>
12 #include <asm/errno.h>
15 #define UNIPHIER_GPIO_PORTS_PER_BANK 8
17 #define UNIPHIER_GPIO_REG_DATA 0 /* data */
18 #define UNIPHIER_GPIO_REG_DIR 4 /* direction (1:in, 0:out) */
20 struct uniphier_gpio_priv {
25 static void uniphier_gpio_offset_write(struct udevice *dev, unsigned offset,
26 unsigned reg, int value)
28 struct uniphier_gpio_priv *priv = dev_get_priv(dev);
31 tmp = readl(priv->base + reg);
36 writel(tmp, priv->base + reg);
39 static int uniphier_gpio_offset_read(struct udevice *dev, unsigned offset,
42 struct uniphier_gpio_priv *priv = dev_get_priv(dev);
44 return !!(readl(priv->base + reg) & BIT(offset));
47 static int uniphier_gpio_direction_input(struct udevice *dev, unsigned offset)
49 uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_REG_DIR, 1);
54 static int uniphier_gpio_direction_output(struct udevice *dev, unsigned offset,
57 uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_REG_DATA, value);
58 uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_REG_DIR, 0);
63 static int uniphier_gpio_get_value(struct udevice *dev, unsigned offset)
65 return uniphier_gpio_offset_read(dev, offset, UNIPHIER_GPIO_REG_DATA);
68 static int uniphier_gpio_set_value(struct udevice *dev, unsigned offset,
71 uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_REG_DATA, value);
76 static int uniphier_gpio_get_function(struct udevice *dev, unsigned offset)
78 return uniphier_gpio_offset_read(dev, offset, UNIPHIER_GPIO_REG_DIR) ?
79 GPIOF_INPUT : GPIOF_OUTPUT;
82 static const struct dm_gpio_ops uniphier_gpio_ops = {
83 .direction_input = uniphier_gpio_direction_input,
84 .direction_output = uniphier_gpio_direction_output,
85 .get_value = uniphier_gpio_get_value,
86 .set_value = uniphier_gpio_set_value,
87 .get_function = uniphier_gpio_get_function,
90 static int uniphier_gpio_probe(struct udevice *dev)
92 struct uniphier_gpio_priv *priv = dev_get_priv(dev);
93 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
94 DECLARE_GLOBAL_DATA_PTR;
99 addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg",
101 if (addr == FDT_ADDR_T_NONE)
104 priv->base = map_sysmem(addr, size);
108 uc_priv->gpio_count = UNIPHIER_GPIO_PORTS_PER_BANK;
110 tmp = (addr & 0xfff);
112 /* Unfortunately, there is a register hole at offset 0x90-0x9f. */
116 snprintf(priv->bank_name, sizeof(priv->bank_name) - 1,
117 "port%d-", (tmp - 8) / 8);
119 uc_priv->bank_name = priv->bank_name;
124 static int uniphier_gpio_remove(struct udevice *dev)
126 struct uniphier_gpio_priv *priv = dev_get_priv(dev);
128 unmap_sysmem(priv->base);
133 /* .data = the number of GPIO banks */
134 static const struct udevice_id uniphier_gpio_match[] = {
135 { .compatible = "socionext,uniphier-gpio" },
139 U_BOOT_DRIVER(uniphier_gpio) = {
140 .name = "uniphier_gpio",
142 .of_match = uniphier_gpio_match,
143 .probe = uniphier_gpio_probe,
144 .remove = uniphier_gpio_remove,
145 .priv_auto_alloc_size = sizeof(struct uniphier_gpio_priv),
146 .ops = &uniphier_gpio_ops,