2 * Copyright (C) 2016-2017 Socionext Inc.
3 * Author: Masahiro Yamada <yamada.masahiro@socionext.com>
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <linux/bitops.h>
12 #include <linux/sizes.h>
13 #include <linux/errno.h>
14 #include <asm/global_data.h>
16 #include <dt-bindings/gpio/uniphier-gpio.h>
18 #define UNIPHIER_GPIO_PORT_DATA 0x0 /* data */
19 #define UNIPHIER_GPIO_PORT_DIR 0x4 /* direction (1:in, 0:out) */
20 #define UNIPHIER_GPIO_IRQ_EN 0x90 /* irq enable */
22 struct uniphier_gpio_priv {
26 static unsigned int uniphier_gpio_bank_to_reg(unsigned int bank)
33 * Unfortunately, the GPIO port registers are not contiguous because
34 * offset 0x90-0x9f is used for IRQ. Add 0x10 when crossing the region.
36 if (reg >= UNIPHIER_GPIO_IRQ_EN)
42 static void uniphier_gpio_get_bank_and_mask(unsigned int offset,
43 unsigned int *bank, u32 *mask)
45 *bank = offset / UNIPHIER_GPIO_LINES_PER_BANK;
46 *mask = BIT(offset % UNIPHIER_GPIO_LINES_PER_BANK);
49 static void uniphier_gpio_reg_update(struct uniphier_gpio_priv *priv,
50 unsigned int reg, u32 mask, u32 val)
54 tmp = readl(priv->regs + reg);
57 writel(tmp, priv->regs + reg);
60 static void uniphier_gpio_bank_write(struct udevice *dev, unsigned int bank,
61 unsigned int reg, u32 mask, u32 val)
63 struct uniphier_gpio_priv *priv = dev_get_priv(dev);
68 uniphier_gpio_reg_update(priv, uniphier_gpio_bank_to_reg(bank) + reg,
72 static void uniphier_gpio_offset_write(struct udevice *dev, unsigned int offset,
73 unsigned int reg, int val)
78 uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
80 uniphier_gpio_bank_write(dev, bank, reg, mask, val ? mask : 0);
83 static int uniphier_gpio_offset_read(struct udevice *dev,
84 unsigned int offset, unsigned int reg)
86 struct uniphier_gpio_priv *priv = dev_get_priv(dev);
87 unsigned int bank, reg_offset;
90 uniphier_gpio_get_bank_and_mask(offset, &bank, &mask);
91 reg_offset = uniphier_gpio_bank_to_reg(bank) + reg;
93 return !!(readl(priv->regs + reg_offset) & mask);
96 static int uniphier_gpio_get_function(struct udevice *dev, unsigned int offset)
98 return uniphier_gpio_offset_read(dev, offset, UNIPHIER_GPIO_PORT_DIR) ?
99 GPIOF_INPUT : GPIOF_OUTPUT;
102 static int uniphier_gpio_direction_input(struct udevice *dev,
105 uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DIR, 1);
110 static int uniphier_gpio_direction_output(struct udevice *dev,
111 unsigned int offset, int value)
113 uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DATA, value);
114 uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DIR, 0);
119 static int uniphier_gpio_get_value(struct udevice *dev, unsigned int offset)
121 return uniphier_gpio_offset_read(dev, offset, UNIPHIER_GPIO_PORT_DATA);
124 static int uniphier_gpio_set_value(struct udevice *dev,
125 unsigned int offset, int value)
127 uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_PORT_DATA, value);
132 static const struct dm_gpio_ops uniphier_gpio_ops = {
133 .direction_input = uniphier_gpio_direction_input,
134 .direction_output = uniphier_gpio_direction_output,
135 .get_value = uniphier_gpio_get_value,
136 .set_value = uniphier_gpio_set_value,
137 .get_function = uniphier_gpio_get_function,
140 static int uniphier_gpio_probe(struct udevice *dev)
142 struct uniphier_gpio_priv *priv = dev_get_priv(dev);
143 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
146 addr = devfdt_get_addr(dev);
147 if (addr == FDT_ADDR_T_NONE)
150 priv->regs = devm_ioremap(dev, addr, SZ_512);
154 uc_priv->gpio_count = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
160 static const struct udevice_id uniphier_gpio_match[] = {
161 { .compatible = "socionext,uniphier-gpio" },
165 U_BOOT_DRIVER(uniphier_gpio) = {
166 .name = "uniphier-gpio",
168 .of_match = uniphier_gpio_match,
169 .probe = uniphier_gpio_probe,
170 .priv_auto_alloc_size = sizeof(struct uniphier_gpio_priv),
171 .ops = &uniphier_gpio_ops,