3 * Mario Six, Guntermann & Drunck GmbH, six@gdsys.de
5 * based on arch/powerpc/include/asm/mpc85xx_gpio.h, which is
7 * Copyright 2010 eXMeritus, A Boeing Company
9 * SPDX-License-Identifier: GPL-2.0+
17 DECLARE_GLOBAL_DATA_PTR;
28 struct mpc85xx_gpio_data {
29 /* The bank's register base in memory */
30 struct ccsr_gpio __iomem *base;
31 /* The address of the registers; used to identify the bank */
33 /* The GPIO count of the bank */
35 /* The GPDAT register cannot be used to determine the value of output
36 * pins on MPC8572/MPC8536, so we shadow it and use the shadowed value
42 inline u32 gpio_mask(uint gpio)
44 return (1U << (31 - (gpio)));
47 static inline u32 mpc85xx_gpio_get_val(struct ccsr_gpio *base, u32 mask)
49 return in_be32(&base->gpdat) & mask;
52 static inline u32 mpc85xx_gpio_get_dir(struct ccsr_gpio *base, u32 mask)
54 return in_be32(&base->gpdir) & mask;
57 static inline void mpc85xx_gpio_set_in(struct ccsr_gpio *base, u32 gpios)
59 clrbits_be32(&base->gpdat, gpios);
60 /* GPDIR register 0 -> input */
61 clrbits_be32(&base->gpdir, gpios);
64 static inline void mpc85xx_gpio_set_low(struct ccsr_gpio *base, u32 gpios)
66 clrbits_be32(&base->gpdat, gpios);
67 /* GPDIR register 1 -> output */
68 setbits_be32(&base->gpdir, gpios);
71 static inline void mpc85xx_gpio_set_high(struct ccsr_gpio *base, u32 gpios)
73 setbits_be32(&base->gpdat, gpios);
74 /* GPDIR register 1 -> output */
75 setbits_be32(&base->gpdir, gpios);
78 static inline int mpc85xx_gpio_open_drain_val(struct ccsr_gpio *base, u32 mask)
80 return in_be32(&base->gpodr) & mask;
83 static inline void mpc85xx_gpio_open_drain_on(struct ccsr_gpio *base, u32
86 /* GPODR register 1 -> open drain on */
87 setbits_be32(&base->gpodr, gpios);
90 static inline void mpc85xx_gpio_open_drain_off(struct ccsr_gpio *base,
93 /* GPODR register 0 -> open drain off (actively driven) */
94 clrbits_be32(&base->gpodr, gpios);
97 static int mpc85xx_gpio_direction_input(struct udevice *dev, uint gpio)
99 struct mpc85xx_gpio_data *data = dev_get_priv(dev);
101 mpc85xx_gpio_set_in(data->base, gpio_mask(gpio));
105 static int mpc85xx_gpio_set_value(struct udevice *dev, uint gpio, int value)
107 struct mpc85xx_gpio_data *data = dev_get_priv(dev);
110 data->dat_shadow |= gpio_mask(gpio);
111 mpc85xx_gpio_set_high(data->base, gpio_mask(gpio));
113 data->dat_shadow &= ~gpio_mask(gpio);
114 mpc85xx_gpio_set_low(data->base, gpio_mask(gpio));
119 static int mpc85xx_gpio_direction_output(struct udevice *dev, uint gpio,
122 return mpc85xx_gpio_set_value(dev, gpio, value);
125 static int mpc85xx_gpio_get_value(struct udevice *dev, uint gpio)
127 struct mpc85xx_gpio_data *data = dev_get_priv(dev);
129 if (!!mpc85xx_gpio_get_dir(data->base, gpio_mask(gpio))) {
130 /* Output -> use shadowed value */
131 return !!(data->dat_shadow & gpio_mask(gpio));
134 /* Input -> read value from GPDAT register */
135 return !!mpc85xx_gpio_get_val(data->base, gpio_mask(gpio));
138 static int mpc85xx_gpio_get_open_drain(struct udevice *dev, uint gpio)
140 struct mpc85xx_gpio_data *data = dev_get_priv(dev);
142 return !!mpc85xx_gpio_open_drain_val(data->base, gpio_mask(gpio));
145 static int mpc85xx_gpio_set_open_drain(struct udevice *dev, uint gpio,
148 struct mpc85xx_gpio_data *data = dev_get_priv(dev);
151 mpc85xx_gpio_open_drain_on(data->base, gpio_mask(gpio));
153 mpc85xx_gpio_open_drain_off(data->base, gpio_mask(gpio));
158 static int mpc85xx_gpio_get_function(struct udevice *dev, uint gpio)
160 struct mpc85xx_gpio_data *data = dev_get_priv(dev);
163 dir = !!mpc85xx_gpio_get_dir(data->base, gpio_mask(gpio));
164 return dir ? GPIOF_OUTPUT : GPIOF_INPUT;
167 #if CONFIG_IS_ENABLED(OF_CONTROL)
168 static int mpc85xx_gpio_ofdata_to_platdata(struct udevice *dev)
170 struct mpc85xx_gpio_plat *plat = dev_get_platdata(dev);
174 addr = fdtdec_get_addr_size_auto_noparent(gd->fdt_blob,
176 "reg", 0, &size, false);
179 plat->ngpios = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
186 static int mpc85xx_gpio_platdata_to_priv(struct udevice *dev)
188 struct mpc85xx_gpio_data *priv = dev_get_priv(dev);
189 struct mpc85xx_gpio_plat *plat = dev_get_platdata(dev);
190 unsigned long size = plat->size;
195 priv->addr = plat->addr;
196 priv->base = map_sysmem(CONFIG_SYS_IMMR + plat->addr, size);
201 priv->gpio_count = plat->ngpios;
202 priv->dat_shadow = 0;
207 static int mpc85xx_gpio_probe(struct udevice *dev)
209 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
210 struct mpc85xx_gpio_data *data = dev_get_priv(dev);
213 mpc85xx_gpio_platdata_to_priv(dev);
215 snprintf(name, sizeof(name), "MPC@%lx_", data->addr);
221 uc_priv->bank_name = str;
222 uc_priv->gpio_count = data->gpio_count;
227 static const struct dm_gpio_ops gpio_mpc85xx_ops = {
228 .direction_input = mpc85xx_gpio_direction_input,
229 .direction_output = mpc85xx_gpio_direction_output,
230 .get_value = mpc85xx_gpio_get_value,
231 .set_value = mpc85xx_gpio_set_value,
232 .get_open_drain = mpc85xx_gpio_get_open_drain,
233 .set_open_drain = mpc85xx_gpio_set_open_drain,
234 .get_function = mpc85xx_gpio_get_function,
237 static const struct udevice_id mpc85xx_gpio_ids[] = {
238 { .compatible = "fsl,pq3-gpio" },
242 U_BOOT_DRIVER(gpio_mpc85xx) = {
243 .name = "gpio_mpc85xx",
245 .ops = &gpio_mpc85xx_ops,
246 #if CONFIG_IS_ENABLED(OF_CONTROL)
247 .ofdata_to_platdata = mpc85xx_gpio_ofdata_to_platdata,
248 .platdata_auto_alloc_size = sizeof(struct mpc85xx_gpio_plat),
249 .of_match = mpc85xx_gpio_ids,
251 .probe = mpc85xx_gpio_probe,
252 .priv_auto_alloc_size = sizeof(struct mpc85xx_gpio_data),