3 * eInfochips Ltd. <www.einfochips.com>
4 * Written-by: Ajay Bhargav <contact@8051projects.net>
7 * Marvell Semiconductor <www.marvell.com>
9 * SPDX-License-Identifier: GPL-2.0+
18 * GPIO Register map for Marvell SOCs
21 u32 gplr; /* Pin Level Register - 0x0000 */
23 u32 gpdr; /* Pin Direction Register - 0x000C */
25 u32 gpsr; /* Pin Output Set Register - 0x0018 */
27 u32 gpcr; /* Pin Output Clear Register - 0x0024 */
29 u32 grer; /* Rising-Edge Detect Enable Register - 0x0030 */
31 u32 gfer; /* Falling-Edge Detect Enable Register - 0x003C */
33 u32 gedr; /* Edge Detect Status Register - 0x0048 */
35 u32 gsdr; /* Bitwise Set of GPIO Direction Register - 0x0054 */
37 u32 gcdr; /* Bitwise Clear of GPIO Direction Register - 0x0060 */
39 u32 gsrer; /* Bitwise Set of Rising-Edge Detect Enable
42 u32 gcrer; /* Bitwise Clear of Rising-Edge Detect Enable
45 u32 gsfer; /* Bitwise Set of Falling-Edge Detect Enable
48 u32 gcfer; /* Bitwise Clear of Falling-Edge Detect Enable
51 u32 apmask; /* Bitwise Mask of Edge Detect Register - 0x009C */
54 #endif /* __MVGPIO_H__ */