2 * Take linux kernel driver drivers/gpio/gpio-pca953x.c for reference.
4 * Copyright (C) 2016 Peng Fan <van.freenix@gmail.com>
6 * SPDX-License-Identifier: GPL-2.0+
12 * The driver's compatible table is borrowed from Linux Kernel,
13 * but now max supported gpio pins is 24 and only PCA953X_TYPE
14 * is supported. PCA957X_TYPE is not supported now.
15 * Also the Polarity Inversion feature is not supported now.
18 * 1. Support PCA957X_TYPE
19 * 2. Support 24 gpio pins
20 * 3. Support Polarity Inversion
31 #include <dt-bindings/gpio/gpio.h>
33 #define PCA953X_INPUT 0
34 #define PCA953X_OUTPUT 1
35 #define PCA953X_INVERT 2
36 #define PCA953X_DIRECTION 3
38 #define PCA_GPIO_MASK 0x00FF
39 #define PCA_INT 0x0100
40 #define PCA953X_TYPE 0x1000
41 #define PCA957X_TYPE 0x2000
42 #define PCA_TYPE_MASK 0xF000
43 #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK)
47 PCA953X_DIRECTION_OUT,
53 DECLARE_GLOBAL_DATA_PTR;
56 * struct pca953x_info - Data for pca953x
58 * @dev: udevice structure for the device
59 * @addr: i2c slave address
60 * @invert: Polarity inversion or not
61 * @gpio_count: the number of gpio pins that the device supports
62 * @chip_type: indicate the chip type,PCA953X or PCA957X
63 * @bank_count: the number of banks that the device supports
64 * @reg_output: array to hold the value of output registers
65 * @reg_direction: array to hold the value of direction registers
74 u8 reg_output[MAX_BANK];
75 u8 reg_direction[MAX_BANK];
78 static int pca953x_write_single(struct udevice *dev, int reg, u8 val,
81 struct pca953x_info *info = dev_get_platdata(dev);
82 int bank_shift = fls((info->gpio_count - 1) / BANK_SZ);
83 int off = offset / BANK_SZ;
86 ret = dm_i2c_write(dev, (reg << bank_shift) + off, &val, 1);
88 dev_err(dev, "%s error\n", __func__);
95 static int pca953x_read_single(struct udevice *dev, int reg, u8 *val,
98 struct pca953x_info *info = dev_get_platdata(dev);
99 int bank_shift = fls((info->gpio_count - 1) / BANK_SZ);
100 int off = offset / BANK_SZ;
104 ret = dm_i2c_read(dev, (reg << bank_shift) + off, &byte, 1);
106 dev_err(dev, "%s error\n", __func__);
115 static int pca953x_read_regs(struct udevice *dev, int reg, u8 *val)
117 struct pca953x_info *info = dev_get_platdata(dev);
120 if (info->gpio_count <= 8) {
121 ret = dm_i2c_read(dev, reg, val, 1);
122 } else if (info->gpio_count <= 16) {
123 ret = dm_i2c_read(dev, reg << 1, val, info->bank_count);
124 } else if (info->gpio_count == 40) {
126 ret = dm_i2c_read(dev, (reg << 3) | 0x80, val, info->bank_count);
128 dev_err(dev, "Unsupported now\n");
135 static int pca953x_is_output(struct udevice *dev, int offset)
137 struct pca953x_info *info = dev_get_platdata(dev);
139 int bank = offset / BANK_SZ;
140 int off = offset % BANK_SZ;
142 /*0: output; 1: input */
143 return !(info->reg_direction[bank] & (1 << off));
146 static int pca953x_get_value(struct udevice *dev, unsigned offset)
151 int off = offset % BANK_SZ;
153 ret = pca953x_read_single(dev, PCA953X_INPUT, &val, offset);
157 return (val >> off) & 0x1;
160 static int pca953x_set_value(struct udevice *dev, unsigned offset,
163 struct pca953x_info *info = dev_get_platdata(dev);
164 int bank = offset / BANK_SZ;
165 int off = offset % BANK_SZ;
170 val = info->reg_output[bank] | (1 << off);
172 val = info->reg_output[bank] & ~(1 << off);
174 ret = pca953x_write_single(dev, PCA953X_OUTPUT, val, offset);
178 info->reg_output[bank] = val;
183 static int pca953x_set_direction(struct udevice *dev, unsigned offset, int dir)
185 struct pca953x_info *info = dev_get_platdata(dev);
186 int bank = offset / BANK_SZ;
187 int off = offset % BANK_SZ;
191 if (dir == PCA953X_DIRECTION_IN)
192 val = info->reg_direction[bank] | (1 << off);
194 val = info->reg_direction[bank] & ~(1 << off);
196 ret = pca953x_write_single(dev, PCA953X_DIRECTION, val, offset);
200 info->reg_direction[bank] = val;
205 static int pca953x_direction_input(struct udevice *dev, unsigned offset)
207 return pca953x_set_direction(dev, offset, PCA953X_DIRECTION_IN);
210 static int pca953x_direction_output(struct udevice *dev, unsigned offset,
213 /* Configure output value. */
214 pca953x_set_value(dev, offset, value);
216 /* Configure direction as output. */
217 pca953x_set_direction(dev, offset, PCA953X_DIRECTION_OUT);
222 static int pca953x_get_function(struct udevice *dev, unsigned offset)
224 if (pca953x_is_output(dev, offset))
230 static int pca953x_xlate(struct udevice *dev, struct gpio_desc *desc,
231 struct ofnode_phandle_args *args)
233 desc->offset = args->args[0];
234 desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
239 static const struct dm_gpio_ops pca953x_ops = {
240 .direction_input = pca953x_direction_input,
241 .direction_output = pca953x_direction_output,
242 .get_value = pca953x_get_value,
243 .set_value = pca953x_set_value,
244 .get_function = pca953x_get_function,
245 .xlate = pca953x_xlate,
248 static int pca953x_probe(struct udevice *dev)
250 struct pca953x_info *info = dev_get_platdata(dev);
251 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
257 addr = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "reg", 0);
263 driver_data = dev_get_driver_data(dev);
265 info->gpio_count = driver_data & PCA_GPIO_MASK;
266 if (info->gpio_count > MAX_BANK * BANK_SZ) {
267 dev_err(dev, "Max support %d pins now\n", MAX_BANK * BANK_SZ);
271 info->chip_type = PCA_CHIP_TYPE(driver_data);
272 if (info->chip_type != PCA953X_TYPE) {
273 dev_err(dev, "Only support PCA953X chip type now.\n");
277 info->bank_count = DIV_ROUND_UP(info->gpio_count, BANK_SZ);
279 ret = pca953x_read_regs(dev, PCA953X_OUTPUT, info->reg_output);
281 dev_err(dev, "Error reading output register\n");
285 ret = pca953x_read_regs(dev, PCA953X_DIRECTION, info->reg_direction);
287 dev_err(dev, "Error reading direction register\n");
291 snprintf(name, sizeof(name), "gpio@%x_", info->addr);
295 uc_priv->bank_name = str;
296 uc_priv->gpio_count = info->gpio_count;
298 dev_dbg(dev, "%s is ready\n", str);
303 #define OF_953X(__nrgpio, __int) (ulong)(__nrgpio | PCA953X_TYPE | __int)
304 #define OF_957X(__nrgpio, __int) (ulong)(__nrgpio | PCA957X_TYPE | __int)
306 static const struct udevice_id pca953x_ids[] = {
307 { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), },
308 { .compatible = "nxp,pca9534", .data = OF_953X(8, PCA_INT), },
309 { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), },
310 { .compatible = "nxp,pca9536", .data = OF_953X(4, 0), },
311 { .compatible = "nxp,pca9537", .data = OF_953X(4, PCA_INT), },
312 { .compatible = "nxp,pca9538", .data = OF_953X(8, PCA_INT), },
313 { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), },
314 { .compatible = "nxp,pca9554", .data = OF_953X(8, PCA_INT), },
315 { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), },
316 { .compatible = "nxp,pca9556", .data = OF_953X(8, 0), },
317 { .compatible = "nxp,pca9557", .data = OF_953X(8, 0), },
318 { .compatible = "nxp,pca9574", .data = OF_957X(8, PCA_INT), },
319 { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), },
320 { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), },
322 { .compatible = "maxim,max7310", .data = OF_953X(8, 0), },
323 { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), },
324 { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), },
325 { .compatible = "maxim,max7315", .data = OF_953X(8, PCA_INT), },
327 { .compatible = "ti,pca6107", .data = OF_953X(8, PCA_INT), },
328 { .compatible = "ti,tca6408", .data = OF_953X(8, PCA_INT), },
329 { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), },
330 { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), },
332 { .compatible = "onsemi,pca9654", .data = OF_953X(8, PCA_INT), },
334 { .compatible = "exar,xra1202", .data = OF_953X(8, 0), },
338 U_BOOT_DRIVER(pca953x) = {
342 .probe = pca953x_probe,
343 .platdata_auto_alloc_size = sizeof(struct pca953x_info),
344 .of_match = pca953x_ids,