2 * Copyright (c) 2015 Microchip Technology Inc
3 * Purna Chandra Mandal <purna.mandal@microchip.com>
5 * SPDX-License-Identifier: GPL-2.0+
14 #include <linux/compat.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <mach/pic32.h>
18 DECLARE_GLOBAL_DATA_PTR;
20 /* Peripheral Pin Control */
21 struct pic32_reg_port {
22 struct pic32_reg_atomic ansel;
23 struct pic32_reg_atomic tris;
24 struct pic32_reg_atomic port;
25 struct pic32_reg_atomic lat;
26 struct pic32_reg_atomic open_drain;
27 struct pic32_reg_atomic cnpu;
28 struct pic32_reg_atomic cnpd;
29 struct pic32_reg_atomic cncon;
33 MICROCHIP_GPIO_DIR_OUT,
34 MICROCHIP_GPIO_DIR_IN,
35 MICROCHIP_GPIOS_PER_BANK = 16,
38 struct pic32_gpio_priv {
39 struct pic32_reg_port *regs;
43 static int pic32_gpio_get_value(struct udevice *dev, unsigned offset)
45 struct pic32_gpio_priv *priv = dev_get_priv(dev);
47 return !!(readl(&priv->regs->port.raw) & BIT(offset));
50 static int pic32_gpio_set_value(struct udevice *dev, unsigned offset,
53 struct pic32_gpio_priv *priv = dev_get_priv(dev);
54 int mask = BIT(offset);
57 writel(mask, &priv->regs->port.set);
59 writel(mask, &priv->regs->port.clr);
64 static int pic32_gpio_direction(struct udevice *dev, unsigned offset)
66 struct pic32_gpio_priv *priv = dev_get_priv(dev);
68 /* pin in analog mode ? */
69 if (readl(&priv->regs->ansel.raw) & BIT(offset))
72 if (readl(&priv->regs->tris.raw) & BIT(offset))
73 return MICROCHIP_GPIO_DIR_IN;
75 return MICROCHIP_GPIO_DIR_OUT;
78 static int pic32_gpio_direction_input(struct udevice *dev, unsigned offset)
80 struct pic32_gpio_priv *priv = dev_get_priv(dev);
81 int mask = BIT(offset);
83 writel(mask, &priv->regs->ansel.clr);
84 writel(mask, &priv->regs->tris.set);
89 static int pic32_gpio_direction_output(struct udevice *dev,
90 unsigned offset, int value)
92 struct pic32_gpio_priv *priv = dev_get_priv(dev);
93 int mask = BIT(offset);
95 writel(mask, &priv->regs->ansel.clr);
96 writel(mask, &priv->regs->tris.clr);
98 pic32_gpio_set_value(dev, offset, value);
102 static int pic32_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
103 struct fdtdec_phandle_args *args)
105 desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
110 static int pic32_gpio_get_function(struct udevice *dev, unsigned offset)
112 int ret = GPIOF_UNUSED;
114 switch (pic32_gpio_direction(dev, offset)) {
115 case MICROCHIP_GPIO_DIR_OUT:
118 case MICROCHIP_GPIO_DIR_IN:
128 static const struct dm_gpio_ops gpio_pic32_ops = {
129 .direction_input = pic32_gpio_direction_input,
130 .direction_output = pic32_gpio_direction_output,
131 .get_value = pic32_gpio_get_value,
132 .set_value = pic32_gpio_set_value,
133 .get_function = pic32_gpio_get_function,
134 .xlate = pic32_gpio_xlate,
137 static int pic32_gpio_probe(struct udevice *dev)
139 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
140 struct pic32_gpio_priv *priv = dev_get_priv(dev);
146 addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", &size);
147 if (addr == FDT_ADDR_T_NONE)
150 priv->regs = ioremap(addr, size);
152 uc_priv->gpio_count = MICROCHIP_GPIOS_PER_BANK;
153 /* extract bank name */
154 end = strrchr(dev->name, '@');
155 bank = trailing_strtoln(dev->name, end);
156 priv->name[0] = 'A' + bank;
157 uc_priv->bank_name = priv->name;
162 static const struct udevice_id pic32_gpio_ids[] = {
163 { .compatible = "microchip,pic32mzda-gpio" },
167 U_BOOT_DRIVER(gpio_pic32) = {
168 .name = "gpio_pic32",
170 .of_match = pic32_gpio_ids,
171 .ops = &gpio_pic32_ops,
172 .probe = pic32_gpio_probe,
173 .priv_auto_alloc_size = sizeof(struct pic32_gpio_priv),