1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2015 Microchip Technology Inc
4 * Purna Chandra Mandal <purna.mandal@microchip.com>
13 #include <linux/compat.h>
14 #include <mach/pic32.h>
16 DECLARE_GLOBAL_DATA_PTR;
18 /* Peripheral Pin Control */
19 struct pic32_reg_port {
20 struct pic32_reg_atomic ansel;
21 struct pic32_reg_atomic tris;
22 struct pic32_reg_atomic port;
23 struct pic32_reg_atomic lat;
24 struct pic32_reg_atomic open_drain;
25 struct pic32_reg_atomic cnpu;
26 struct pic32_reg_atomic cnpd;
27 struct pic32_reg_atomic cncon;
31 MICROCHIP_GPIO_DIR_OUT,
32 MICROCHIP_GPIO_DIR_IN,
33 MICROCHIP_GPIOS_PER_BANK = 16,
36 struct pic32_gpio_priv {
37 struct pic32_reg_port *regs;
41 static int pic32_gpio_get_value(struct udevice *dev, unsigned offset)
43 struct pic32_gpio_priv *priv = dev_get_priv(dev);
45 return !!(readl(&priv->regs->port.raw) & BIT(offset));
48 static int pic32_gpio_set_value(struct udevice *dev, unsigned offset,
51 struct pic32_gpio_priv *priv = dev_get_priv(dev);
52 int mask = BIT(offset);
55 writel(mask, &priv->regs->port.set);
57 writel(mask, &priv->regs->port.clr);
62 static int pic32_gpio_direction(struct udevice *dev, unsigned offset)
64 struct pic32_gpio_priv *priv = dev_get_priv(dev);
66 /* pin in analog mode ? */
67 if (readl(&priv->regs->ansel.raw) & BIT(offset))
70 if (readl(&priv->regs->tris.raw) & BIT(offset))
71 return MICROCHIP_GPIO_DIR_IN;
73 return MICROCHIP_GPIO_DIR_OUT;
76 static int pic32_gpio_direction_input(struct udevice *dev, unsigned offset)
78 struct pic32_gpio_priv *priv = dev_get_priv(dev);
79 int mask = BIT(offset);
81 writel(mask, &priv->regs->ansel.clr);
82 writel(mask, &priv->regs->tris.set);
87 static int pic32_gpio_direction_output(struct udevice *dev,
88 unsigned offset, int value)
90 struct pic32_gpio_priv *priv = dev_get_priv(dev);
91 int mask = BIT(offset);
93 writel(mask, &priv->regs->ansel.clr);
94 writel(mask, &priv->regs->tris.clr);
96 pic32_gpio_set_value(dev, offset, value);
100 static int pic32_gpio_get_function(struct udevice *dev, unsigned offset)
102 int ret = GPIOF_UNUSED;
104 switch (pic32_gpio_direction(dev, offset)) {
105 case MICROCHIP_GPIO_DIR_OUT:
108 case MICROCHIP_GPIO_DIR_IN:
118 static const struct dm_gpio_ops gpio_pic32_ops = {
119 .direction_input = pic32_gpio_direction_input,
120 .direction_output = pic32_gpio_direction_output,
121 .get_value = pic32_gpio_get_value,
122 .set_value = pic32_gpio_set_value,
123 .get_function = pic32_gpio_get_function,
126 static int pic32_gpio_probe(struct udevice *dev)
128 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
129 struct pic32_gpio_priv *priv = dev_get_priv(dev);
135 addr = fdtdec_get_addr_size(gd->fdt_blob, dev_of_offset(dev), "reg",
137 if (addr == FDT_ADDR_T_NONE)
140 priv->regs = ioremap(addr, size);
142 uc_priv->gpio_count = MICROCHIP_GPIOS_PER_BANK;
143 /* extract bank name */
144 end = strrchr(dev->name, '@');
145 bank = trailing_strtoln(dev->name, end);
146 priv->name[0] = 'A' + bank;
147 uc_priv->bank_name = priv->name;
152 static const struct udevice_id pic32_gpio_ids[] = {
153 { .compatible = "microchip,pic32mzda-gpio" },
157 U_BOOT_DRIVER(gpio_pic32) = {
158 .name = "gpio_pic32",
160 .of_match = pic32_gpio_ids,
161 .ops = &gpio_pic32_ops,
162 .probe = pic32_gpio_probe,
163 .priv_auto_alloc_size = sizeof(struct pic32_gpio_priv),