2 * (C) Copyright 2009 Samsung Electronics
3 * Minkyu Kang <mk7.kang@samsung.com>
5 * SPDX-License-Identifier: GPL-2.0+
12 #define S5P_GPIO_GET_PIN(x) (x % GPIO_PER_BANK)
14 #define CON_MASK(x) (0xf << ((x) << 2))
15 #define CON_SFR(x, v) ((v) << ((x) << 2))
17 #define DAT_MASK(x) (0x1 << (x))
18 #define DAT_SET(x) (0x1 << (x))
20 #define PULL_MASK(x) (0x3 << ((x) << 1))
21 #define PULL_MODE(x, v) ((v) << ((x) << 1))
23 #define DRV_MASK(x) (0x3 << ((x) << 1))
24 #define DRV_SET(x, m) ((m) << ((x) << 1))
25 #define RATE_MASK(x) (0x1 << (x + 16))
26 #define RATE_SET(x) (0x1 << (x + 16))
28 #define name_to_gpio(n) s5p_name_to_gpio(n)
29 static inline int s5p_name_to_gpio(const char *name)
31 unsigned num, irregular_set_number, irregular_bank_base;
32 const struct gpio_name_num_table *tabp;
33 char this_bank, bank_name, irregular_bank_name;
37 * The gpio name starts with either 'g' or 'gp' followed by the bank
38 * name character. Skip one or two characters depending on the prefix.
40 if (name[0] == 'g' && name[1] == 'p')
42 else if (name[0] == 'g')
45 return -1; /* Name must start with 'g' */
49 return -1; /* At least one digit is required/expected. */
52 * On both exynos5 and exynos5420 architectures there is a bank of
53 * GPIOs which does not fall into the regular address pattern. Those
54 * banks are c4 on Exynos5 and y7 on Exynos5420. The rest of the below
55 * assignments help to handle these irregularities.
57 #if defined(CONFIG_EXYNOS4) || defined(CONFIG_EXYNOS5)
58 if (cpu_is_exynos5()) {
59 if (proid_is_exynos5420()) {
60 tabp = exynos5420_gpio_table;
61 irregular_bank_name = 'y';
62 irregular_set_number = '7';
63 irregular_bank_base = EXYNOS5420_GPIO_Y70;
65 tabp = exynos5_gpio_table;
66 irregular_bank_name = 'c';
67 irregular_set_number = '4';
68 irregular_bank_base = EXYNOS5_GPIO_C40;
71 if (proid_is_exynos4412())
72 tabp = exynos4x12_gpio_table;
74 tabp = exynos4_gpio_table;
75 irregular_bank_name = 0;
76 irregular_set_number = 0;
77 irregular_bank_base = 0;
81 tabp = s5pc110_gpio_table;
83 tabp = s5pc100_gpio_table;
84 irregular_bank_name = 0;
85 irregular_set_number = 0;
86 irregular_bank_base = 0;
89 this_bank = tabp->bank;
91 if (bank_name == this_bank) {
92 unsigned pin_index; /* pin number within the bank */
93 if ((bank_name == irregular_bank_name) &&
94 (name[0] == irregular_set_number)) {
95 pin_index = name[1] - '0';
96 /* Irregular sets have 8 pins. */
97 if (pin_index >= GPIO_PER_BANK)
99 num = irregular_bank_base + pin_index;
101 pin_index = simple_strtoul(name, &endp, 8);
102 pin_index -= tabp->bank_offset;
104 * Sanity check: bunk 'z' has no set number,
105 * for all other banks there must be exactly
106 * two octal digits, and the resulting number
107 * should not exceed the number of pins in the
110 if (((bank_name != 'z') && !name[1]) ||
112 (pin_index >= tabp->bank_size))
114 num = tabp->base + pin_index;
118 this_bank = (++tabp)->bank;
124 static void s5p_gpio_cfg_pin(struct s5p_gpio_bank *bank, int gpio, int cfg)
128 value = readl(&bank->con);
129 value &= ~CON_MASK(gpio);
130 value |= CON_SFR(gpio, cfg);
131 writel(value, &bank->con);
134 static void s5p_gpio_set_value(struct s5p_gpio_bank *bank, int gpio, int en)
138 value = readl(&bank->dat);
139 value &= ~DAT_MASK(gpio);
141 value |= DAT_SET(gpio);
142 writel(value, &bank->dat);
145 static void s5p_gpio_direction_output(struct s5p_gpio_bank *bank,
148 s5p_gpio_cfg_pin(bank, gpio, S5P_GPIO_OUTPUT);
149 s5p_gpio_set_value(bank, gpio, en);
152 static void s5p_gpio_direction_input(struct s5p_gpio_bank *bank, int gpio)
154 s5p_gpio_cfg_pin(bank, gpio, S5P_GPIO_INPUT);
157 static unsigned int s5p_gpio_get_value(struct s5p_gpio_bank *bank, int gpio)
161 value = readl(&bank->dat);
162 return !!(value & DAT_MASK(gpio));
165 static void s5p_gpio_set_pull(struct s5p_gpio_bank *bank, int gpio, int mode)
169 value = readl(&bank->pull);
170 value &= ~PULL_MASK(gpio);
173 case S5P_GPIO_PULL_DOWN:
174 case S5P_GPIO_PULL_UP:
175 value |= PULL_MODE(gpio, mode);
181 writel(value, &bank->pull);
184 static void s5p_gpio_set_drv(struct s5p_gpio_bank *bank, int gpio, int mode)
188 value = readl(&bank->drv);
189 value &= ~DRV_MASK(gpio);
192 case S5P_GPIO_DRV_1X:
193 case S5P_GPIO_DRV_2X:
194 case S5P_GPIO_DRV_3X:
195 case S5P_GPIO_DRV_4X:
196 value |= DRV_SET(gpio, mode);
202 writel(value, &bank->drv);
205 static void s5p_gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode)
209 value = readl(&bank->drv);
210 value &= ~RATE_MASK(gpio);
213 case S5P_GPIO_DRV_FAST:
214 case S5P_GPIO_DRV_SLOW:
215 value |= RATE_SET(gpio);
221 writel(value, &bank->drv);
224 static struct s5p_gpio_bank *s5p_gpio_get_bank(unsigned int gpio)
226 const struct gpio_info *data;
230 data = get_gpio_data();
231 count = get_bank_num();
234 for (i = 0; i < count; i++) {
235 debug("i=%d, upto=%d\n", i, upto);
236 if (gpio < data->max_gpio) {
237 struct s5p_gpio_bank *bank;
238 bank = (struct s5p_gpio_bank *)data->reg_addr;
239 bank += (gpio - upto) / GPIO_PER_BANK;
240 debug("gpio=%d, bank=%p\n", gpio, bank);
244 upto = data->max_gpio;
251 int s5p_gpio_get_pin(unsigned gpio)
253 return S5P_GPIO_GET_PIN(gpio);
256 /* Common GPIO API */
258 int gpio_request(unsigned gpio, const char *label)
263 int gpio_free(unsigned gpio)
268 int gpio_direction_input(unsigned gpio)
270 s5p_gpio_direction_input(s5p_gpio_get_bank(gpio),
271 s5p_gpio_get_pin(gpio));
275 int gpio_direction_output(unsigned gpio, int value)
277 s5p_gpio_direction_output(s5p_gpio_get_bank(gpio),
278 s5p_gpio_get_pin(gpio), value);
282 int gpio_get_value(unsigned gpio)
284 return (int) s5p_gpio_get_value(s5p_gpio_get_bank(gpio),
285 s5p_gpio_get_pin(gpio));
288 int gpio_set_value(unsigned gpio, int value)
290 s5p_gpio_set_value(s5p_gpio_get_bank(gpio),
291 s5p_gpio_get_pin(gpio), value);
296 void gpio_set_pull(int gpio, int mode)
298 s5p_gpio_set_pull(s5p_gpio_get_bank(gpio),
299 s5p_gpio_get_pin(gpio), mode);
302 void gpio_set_drv(int gpio, int mode)
304 s5p_gpio_set_drv(s5p_gpio_get_bank(gpio),
305 s5p_gpio_get_pin(gpio), mode);
308 void gpio_cfg_pin(int gpio, int cfg)
310 s5p_gpio_cfg_pin(s5p_gpio_get_bank(gpio),
311 s5p_gpio_get_pin(gpio), cfg);
314 void gpio_set_rate(int gpio, int mode)
316 s5p_gpio_set_rate(s5p_gpio_get_bank(gpio),
317 s5p_gpio_get_pin(gpio), mode);