3 * Yuri Tikhonov, Emcraft Systems, yur@emcraft.com
6 * Kamil Lulko, <kamil.lulko@gmail.com>
8 * Copyright 2015 ATS Advanced Telematics Systems GmbH
9 * Copyright 2015 Konsulko Group, Matt Porter <mporter@konsulko.com>
11 * SPDX-License-Identifier: GPL-2.0+
16 #include <linux/errno.h>
17 #include <asm/arch/stm32.h>
18 #include <asm/arch/gpio.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 static const unsigned long io_base[] = {
23 STM32_GPIOA_BASE, STM32_GPIOB_BASE, STM32_GPIOC_BASE,
24 STM32_GPIOD_BASE, STM32_GPIOE_BASE, STM32_GPIOF_BASE,
25 STM32_GPIOG_BASE, STM32_GPIOH_BASE, STM32_GPIOI_BASE
28 struct stm32_gpio_regs {
29 u32 moder; /* GPIO port mode */
30 u32 otyper; /* GPIO port output type */
31 u32 ospeedr; /* GPIO port output speed */
32 u32 pupdr; /* GPIO port pull-up/pull-down */
33 u32 idr; /* GPIO port input data */
34 u32 odr; /* GPIO port output data */
35 u32 bsrr; /* GPIO port bit set/reset */
36 u32 lckr; /* GPIO port configuration lock */
37 u32 afr[2]; /* GPIO alternate function */
40 #define CHECK_DSC(x) (!x || x->port > 8 || x->pin > 15)
41 #define CHECK_CTL(x) (!x || x->af > 15 || x->mode > 3 || x->otype > 1 || \
42 x->pupd > 2 || x->speed > 3)
44 int stm32_gpio_config(const struct stm32_gpio_dsc *dsc,
45 const struct stm32_gpio_ctl *ctl)
47 struct stm32_gpio_regs *gpio_regs;
60 gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
62 i = (dsc->pin & 0x07) * 4;
63 clrsetbits_le32(&gpio_regs->afr[dsc->pin >> 3], 0xF << i, ctl->af << i);
67 clrsetbits_le32(&gpio_regs->moder, 0x3 << i, ctl->mode << i);
68 clrsetbits_le32(&gpio_regs->otyper, 0x3 << i, ctl->otype << i);
69 clrsetbits_le32(&gpio_regs->ospeedr, 0x3 << i, ctl->speed << i);
70 clrsetbits_le32(&gpio_regs->pupdr, 0x3 << i, ctl->pupd << i);
77 int stm32_gpout_set(const struct stm32_gpio_dsc *dsc, int state)
79 struct stm32_gpio_regs *gpio_regs;
87 gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
90 writel(1 << dsc->pin, &gpio_regs->bsrr);
92 writel(1 << (dsc->pin + 16), &gpio_regs->bsrr);
99 int stm32_gpin_get(const struct stm32_gpio_dsc *dsc)
101 struct stm32_gpio_regs *gpio_regs;
104 if (CHECK_DSC(dsc)) {
109 gpio_regs = (struct stm32_gpio_regs *)io_base[dsc->port];
110 rv = readl(&gpio_regs->idr) & (1 << dsc->pin);
115 /* Common GPIO API */
117 int gpio_request(unsigned gpio, const char *label)
122 int gpio_free(unsigned gpio)
127 int gpio_direction_input(unsigned gpio)
129 struct stm32_gpio_dsc dsc;
130 struct stm32_gpio_ctl ctl;
132 dsc.port = stm32_gpio_to_port(gpio);
133 dsc.pin = stm32_gpio_to_pin(gpio);
134 ctl.af = STM32_GPIO_AF0;
135 ctl.mode = STM32_GPIO_MODE_IN;
136 ctl.otype = STM32_GPIO_OTYPE_PP;
137 ctl.pupd = STM32_GPIO_PUPD_NO;
138 ctl.speed = STM32_GPIO_SPEED_50M;
140 return stm32_gpio_config(&dsc, &ctl);
143 int gpio_direction_output(unsigned gpio, int value)
145 struct stm32_gpio_dsc dsc;
146 struct stm32_gpio_ctl ctl;
149 dsc.port = stm32_gpio_to_port(gpio);
150 dsc.pin = stm32_gpio_to_pin(gpio);
151 ctl.af = STM32_GPIO_AF0;
152 ctl.mode = STM32_GPIO_MODE_OUT;
153 ctl.pupd = STM32_GPIO_PUPD_NO;
154 ctl.speed = STM32_GPIO_SPEED_50M;
156 res = stm32_gpio_config(&dsc, &ctl);
159 res = stm32_gpout_set(&dsc, value);
164 int gpio_get_value(unsigned gpio)
166 struct stm32_gpio_dsc dsc;
168 dsc.port = stm32_gpio_to_port(gpio);
169 dsc.pin = stm32_gpio_to_pin(gpio);
171 return stm32_gpin_get(&dsc);
174 int gpio_set_value(unsigned gpio, int value)
176 struct stm32_gpio_dsc dsc;
178 dsc.port = stm32_gpio_to_port(gpio);
179 dsc.pin = stm32_gpio_to_pin(gpio);
181 return stm32_gpout_set(&dsc, value);