1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2010-2016, NVIDIA CORPORATION.
4 * (based on tegra_gpio.c)
13 #include <asm/bitops.h>
15 #include <dm/device-internal.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include "tegra186_gpio_priv.h"
19 struct tegra186_gpio_port_data {
24 struct tegra186_gpio_ctlr_data {
25 const struct tegra186_gpio_port_data *ports;
29 struct tegra186_gpio_platdata {
34 static uint32_t *tegra186_gpio_reg(struct udevice *dev, uint32_t reg,
37 struct tegra186_gpio_platdata *plat = dev->platdata;
38 uint32_t index = (reg + (gpio * TEGRA186_GPIO_PER_GPIO_STRIDE)) / 4;
40 return &(plat->regs[index]);
43 static int tegra186_gpio_set_out(struct udevice *dev, unsigned offset,
49 reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_OUTPUT_CONTROL, offset);
52 rval &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
54 rval |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
57 reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_ENABLE_CONFIG, offset);
60 rval |= TEGRA186_GPIO_ENABLE_CONFIG_OUT;
62 rval &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT;
63 rval |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
69 static int tegra186_gpio_set_val(struct udevice *dev, unsigned offset, bool val)
74 reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_OUTPUT_VALUE, offset);
77 rval |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
79 rval &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
85 static int tegra186_gpio_direction_input(struct udevice *dev, unsigned offset)
87 return tegra186_gpio_set_out(dev, offset, false);
90 static int tegra186_gpio_direction_output(struct udevice *dev, unsigned offset,
95 ret = tegra186_gpio_set_val(dev, offset, value != 0);
98 return tegra186_gpio_set_out(dev, offset, true);
101 static int tegra186_gpio_get_value(struct udevice *dev, unsigned offset)
106 reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_ENABLE_CONFIG, offset);
109 if (rval & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
110 reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_OUTPUT_VALUE,
113 reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_INPUT, offset);
119 static int tegra186_gpio_set_value(struct udevice *dev, unsigned offset,
122 return tegra186_gpio_set_val(dev, offset, value != 0);
125 static int tegra186_gpio_get_function(struct udevice *dev, unsigned offset)
130 reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_ENABLE_CONFIG, offset);
132 if (rval & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
138 static int tegra186_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
139 struct ofnode_phandle_args *args)
143 gpio = args->args[0];
144 port = gpio / TEGRA186_GPIO_PER_GPIO_COUNT;
145 ret = device_get_child(dev, port, &desc->dev);
148 desc->offset = gpio % TEGRA186_GPIO_PER_GPIO_COUNT;
149 desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
154 static const struct dm_gpio_ops tegra186_gpio_ops = {
155 .direction_input = tegra186_gpio_direction_input,
156 .direction_output = tegra186_gpio_direction_output,
157 .get_value = tegra186_gpio_get_value,
158 .set_value = tegra186_gpio_set_value,
159 .get_function = tegra186_gpio_get_function,
160 .xlate = tegra186_gpio_xlate,
164 * We have a top-level GPIO device with no actual GPIOs. It has a child device
165 * for each port within the controller.
167 static int tegra186_gpio_bind(struct udevice *parent)
169 struct tegra186_gpio_platdata *parent_plat = parent->platdata;
170 struct tegra186_gpio_ctlr_data *ctlr_data =
171 (struct tegra186_gpio_ctlr_data *)dev_get_driver_data(parent);
175 /* If this is a child device, there is nothing to do here */
179 regs = (uint32_t *)devfdt_get_addr_name(parent, "gpio");
180 if (regs == (uint32_t *)FDT_ADDR_T_NONE)
183 for (port = 0; port < ctlr_data->port_count; port++) {
184 struct tegra186_gpio_platdata *plat;
187 plat = calloc(1, sizeof(*plat));
190 plat->name = ctlr_data->ports[port].name;
191 plat->regs = &(regs[ctlr_data->ports[port].offset / 4]);
193 ret = device_bind(parent, parent->driver, plat->name, plat,
197 dev_set_of_offset(dev, dev_of_offset(parent));
203 static int tegra186_gpio_probe(struct udevice *dev)
205 struct tegra186_gpio_platdata *plat = dev->platdata;
206 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
208 /* Only child devices have ports */
212 uc_priv->gpio_count = TEGRA186_GPIO_PER_GPIO_COUNT;
213 uc_priv->bank_name = plat->name;
218 static const struct tegra186_gpio_port_data tegra186_gpio_main_ports[] = {
244 static const struct tegra186_gpio_ctlr_data tegra186_gpio_main_data = {
245 .ports = tegra186_gpio_main_ports,
246 .port_count = ARRAY_SIZE(tegra186_gpio_main_ports),
249 static const struct tegra186_gpio_port_data tegra186_gpio_aon_ports[] = {
260 static const struct tegra186_gpio_ctlr_data tegra186_gpio_aon_data = {
261 .ports = tegra186_gpio_aon_ports,
262 .port_count = ARRAY_SIZE(tegra186_gpio_aon_ports),
265 static const struct udevice_id tegra186_gpio_ids[] = {
267 .compatible = "nvidia,tegra186-gpio",
268 .data = (ulong)&tegra186_gpio_main_data,
271 .compatible = "nvidia,tegra186-gpio-aon",
272 .data = (ulong)&tegra186_gpio_aon_data,
277 U_BOOT_DRIVER(tegra186_gpio) = {
278 .name = "tegra186_gpio",
280 .of_match = tegra186_gpio_ids,
281 .bind = tegra186_gpio_bind,
282 .probe = tegra186_gpio_probe,
283 .ops = &tegra186_gpio_ops,
284 .flags = DM_FLAG_PRE_RELOC,