2 * Copyright (c) 2010-2016, NVIDIA CORPORATION.
3 * (based on tegra_gpio.c)
5 * SPDX-License-Identifier: GPL-2.0
14 #include <asm/bitops.h>
16 #include <dm/device-internal.h>
17 #include <dt-bindings/gpio/gpio.h>
18 #include "tegra186_gpio_priv.h"
20 struct tegra186_gpio_port_data {
25 struct tegra186_gpio_ctlr_data {
26 const struct tegra186_gpio_port_data *ports;
30 struct tegra186_gpio_platdata {
35 static uint32_t *tegra186_gpio_reg(struct udevice *dev, uint32_t reg,
38 struct tegra186_gpio_platdata *plat = dev->platdata;
39 uint32_t index = (reg + (gpio * TEGRA186_GPIO_PER_GPIO_STRIDE)) / 4;
41 return &(plat->regs[index]);
44 static int tegra186_gpio_set_out(struct udevice *dev, unsigned offset,
50 reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_OUTPUT_CONTROL, offset);
53 rval &= ~TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
55 rval |= TEGRA186_GPIO_OUTPUT_CONTROL_FLOATED;
58 reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_ENABLE_CONFIG, offset);
61 rval |= TEGRA186_GPIO_ENABLE_CONFIG_OUT;
63 rval &= ~TEGRA186_GPIO_ENABLE_CONFIG_OUT;
64 rval |= TEGRA186_GPIO_ENABLE_CONFIG_ENABLE;
70 static int tegra186_gpio_set_val(struct udevice *dev, unsigned offset, bool val)
75 reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_OUTPUT_VALUE, offset);
78 rval |= TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
80 rval &= ~TEGRA186_GPIO_OUTPUT_VALUE_HIGH;
86 static int tegra186_gpio_direction_input(struct udevice *dev, unsigned offset)
88 return tegra186_gpio_set_out(dev, offset, false);
91 static int tegra186_gpio_direction_output(struct udevice *dev, unsigned offset,
96 ret = tegra186_gpio_set_val(dev, offset, value != 0);
99 return tegra186_gpio_set_out(dev, offset, true);
102 static int tegra186_gpio_get_value(struct udevice *dev, unsigned offset)
107 reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_ENABLE_CONFIG, offset);
110 if (rval & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
111 reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_OUTPUT_VALUE,
114 reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_INPUT, offset);
120 static int tegra186_gpio_set_value(struct udevice *dev, unsigned offset,
123 return tegra186_gpio_set_val(dev, offset, value != 0);
126 static int tegra186_gpio_get_function(struct udevice *dev, unsigned offset)
131 reg = tegra186_gpio_reg(dev, TEGRA186_GPIO_ENABLE_CONFIG, offset);
133 if (rval & TEGRA186_GPIO_ENABLE_CONFIG_OUT)
139 static int tegra186_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
140 struct ofnode_phandle_args *args)
144 gpio = args->args[0];
145 port = gpio / TEGRA186_GPIO_PER_GPIO_COUNT;
146 ret = device_get_child(dev, port, &desc->dev);
149 desc->offset = gpio % TEGRA186_GPIO_PER_GPIO_COUNT;
150 desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
155 static const struct dm_gpio_ops tegra186_gpio_ops = {
156 .direction_input = tegra186_gpio_direction_input,
157 .direction_output = tegra186_gpio_direction_output,
158 .get_value = tegra186_gpio_get_value,
159 .set_value = tegra186_gpio_set_value,
160 .get_function = tegra186_gpio_get_function,
161 .xlate = tegra186_gpio_xlate,
165 * We have a top-level GPIO device with no actual GPIOs. It has a child device
166 * for each port within the controller.
168 static int tegra186_gpio_bind(struct udevice *parent)
170 struct tegra186_gpio_platdata *parent_plat = parent->platdata;
171 struct tegra186_gpio_ctlr_data *ctlr_data =
172 (struct tegra186_gpio_ctlr_data *)dev_get_driver_data(parent);
176 /* If this is a child device, there is nothing to do here */
180 regs = (uint32_t *)devfdt_get_addr_name(parent, "gpio");
181 if (regs == (uint32_t *)FDT_ADDR_T_NONE)
184 for (port = 0; port < ctlr_data->port_count; port++) {
185 struct tegra186_gpio_platdata *plat;
188 plat = calloc(1, sizeof(*plat));
191 plat->name = ctlr_data->ports[port].name;
192 plat->regs = &(regs[ctlr_data->ports[port].offset / 4]);
194 ret = device_bind(parent, parent->driver, plat->name, plat,
198 dev_set_of_offset(dev, dev_of_offset(parent));
204 static int tegra186_gpio_probe(struct udevice *dev)
206 struct tegra186_gpio_platdata *plat = dev->platdata;
207 struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
209 /* Only child devices have ports */
213 uc_priv->gpio_count = TEGRA186_GPIO_PER_GPIO_COUNT;
214 uc_priv->bank_name = plat->name;
219 static const struct tegra186_gpio_port_data tegra186_gpio_main_ports[] = {
245 static const struct tegra186_gpio_ctlr_data tegra186_gpio_main_data = {
246 .ports = tegra186_gpio_main_ports,
247 .port_count = ARRAY_SIZE(tegra186_gpio_main_ports),
250 static const struct tegra186_gpio_port_data tegra186_gpio_aon_ports[] = {
261 static const struct tegra186_gpio_ctlr_data tegra186_gpio_aon_data = {
262 .ports = tegra186_gpio_aon_ports,
263 .port_count = ARRAY_SIZE(tegra186_gpio_aon_ports),
266 static const struct udevice_id tegra186_gpio_ids[] = {
268 .compatible = "nvidia,tegra186-gpio",
269 .data = (ulong)&tegra186_gpio_main_data,
272 .compatible = "nvidia,tegra186-gpio-aon",
273 .data = (ulong)&tegra186_gpio_aon_data,
278 U_BOOT_DRIVER(tegra186_gpio) = {
279 .name = "tegra186_gpio",
281 .of_match = tegra186_gpio_ids,
282 .bind = tegra186_gpio_bind,
283 .probe = tegra186_gpio_probe,
284 .ops = &tegra186_gpio_ops,
285 .flags = DM_FLAG_PRE_RELOC,