2 # I2C subsystem configuration
8 bool "Enable Driver Model for I2C drivers"
11 Enable driver model for I2C. The I2C uclass interface: probe, read,
12 write and speed, is implemented with the bus drivers operations,
13 which provide methods for bus setting and data transfer. Each chip
14 device (bus child) info is kept as parent platdata. The interface
15 is defined in include/i2c.h. When i2c bus driver supports the i2c
16 uclass, but the device drivers not, then DM_I2C_COMPAT config can
17 be used as compatibility layer.
20 bool "Enable I2C compatibility layer"
23 Enable old-style I2C functions for compatibility with existing code.
24 This option can be enabled as a temporary measure to avoid needing
25 to convert all code for a board in a single commit. It should not
26 be enabled for any board in an official release.
28 config I2C_CROS_EC_TUNNEL
29 tristate "Chrome OS EC tunnel I2C bus"
32 This provides an I2C bus that will tunnel i2c commands through to
33 the other side of the Chrome OS EC to the I2C bus connected there.
34 This will work whatever the interface used to talk to the EC (SPI,
35 I2C or LPC). Some Chromebooks use this when the hardware design
36 does not allow direct access to the main PMIC from the AP.
38 config I2C_CROS_EC_LDO
39 bool "Provide access to LDOs on the Chrome OS EC"
42 On many Chromebooks the main PMIC is inaccessible to the AP. This is
43 often dealt with by using an I2C pass-through interface provided by
44 the EC. On some unfortunate models (e.g. Spring) the pass-through
45 is not available, and an LDO message is available instead. This
46 option enables a driver which provides very basic access to those
47 regulators, via the EC. We implement this as an I2C bus which
48 emulates just the TPS65090 messages we know about. This is done to
49 avoid duplicating the logic in the TPS65090 regulator driver for
50 enabling/disabling an LDO.
53 bool "Enable Driver Model for software emulated I2C bus driver"
54 depends on DM_I2C && DM_GPIO
56 Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO
57 configuration is given by the device tree. Kernel-style device tree
58 bindings are supported.
59 Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
62 bool "Atmel I2C driver"
63 depends on DM_I2C && ARCH_AT91
65 Add support for the Atmel I2C driver. A serious problem is that there
66 is no documented way to issue repeated START conditions for more than
67 two messages, as needed to support combined I2C messages. Use the
68 i2c-gpio driver unless your system can cope with this limitation.
69 Binding info: doc/device-tree-bindings/i2c/i2c-at91.txt
72 bool "Freescale I2C bus driver"
75 Add support for Freescale I2C busses as used on MPC8240, MPC8245, and
78 config SYS_I2C_CADENCE
79 tristate "Cadence I2C Controller"
80 depends on DM_I2C && (ARCH_ZYNQ || ARM64)
82 Say yes here to select Cadence I2C Host Controller. This controller is
83 e.g. used by Xilinx Zynq.
86 bool "Designware I2C Controller"
89 Say yes here to select the Designware I2C Host Controller. This
90 controller is used in various SoCs, e.g. the ST SPEAr, Altera
91 SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs.
93 config SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
94 bool "DW I2C Enable Status Register not supported"
95 depends on SYS_I2C_DW && (TARGET_SPEAR300 || TARGET_SPEAR310 || \
96 TARGET_SPEAR320 || TARGET_SPEAR600 || TARGET_X600)
99 Some versions of the Designware I2C controller do not support the
100 enable status register. This config option can be enabled in such
104 bool "Intel I2C/SMBUS driver"
107 Add support for the Intel SMBUS driver. So far this driver is just
108 a stub which perhaps some basic init. There is no implementation of
109 the I2C API meaning that any I2C operations will immediately fail
112 config SYS_I2C_ROCKCHIP
113 bool "Rockchip I2C driver"
116 Add support for the Rockchip I2C driver. This is used with various
117 Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips
118 have several I2C ports and all are provided, controled by the
121 config SYS_I2C_SANDBOX
122 bool "Sandbox I2C driver"
123 depends on SANDBOX && DM_I2C
125 Enable I2C support for sandbox. This is an emulation of a real I2C
126 bus. Devices can be attached to the bus using the device tree
127 which specifies the driver to use. As an example, see this device
128 tree fragment from sandbox.dts. It shows that the I2C bus has a
129 single EEPROM at address 0x2c (7-bit address) which is emulated by
130 the driver for "sandbox,i2c-eeprom", which is in
131 drivers/misc/i2c_eeprom_emul.c.
134 #address-cells = <1>;
137 compatible = "sandbox,i2c";
138 clock-frequency = <400000>;
141 compatible = "i2c-eeprom";
143 compatible = "sandbox,i2c-eeprom";
144 sandbox,filename = "i2c.bin";
145 sandbox,size = <128>;
151 config SYS_I2C_UNIPHIER
152 bool "UniPhier I2C driver"
153 depends on ARCH_UNIPHIER && DM_I2C
156 Support for UniPhier I2C controller driver. This I2C controller
157 is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs.
159 config SYS_I2C_UNIPHIER_F
160 bool "UniPhier FIFO-builtin I2C driver"
161 depends on ARCH_UNIPHIER && DM_I2C
164 Support for UniPhier FIFO-builtin I2C controller driver.
165 This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs.
167 config SYS_I2C_MVTWSI
168 bool "Marvell I2C driver"
171 Support for Marvell I2C controllers as used on the orion5x and
172 kirkwood SoC families.
174 config TEGRA186_BPMP_I2C
175 bool "Enable Tegra186 BPMP-based I2C driver"
176 depends on TEGRA186_BPMP
178 Support for Tegra I2C controllers managed by the BPMP (Boot and
179 Power Management Processor). On Tegra186, some I2C controllers are
180 directly controlled by the main CPU, whereas others are controlled
181 by the BPMP, and can only be accessed by the main CPU via IPC
182 requests to the BPMP. This driver covers the latter case.
184 source "drivers/i2c/muxes/Kconfig"