2 * TI DaVinci (TMS320DM644x) I2C driver.
4 * (C) Copyright 2012-2014
5 * Texas Instruments Incorporated, <www.ti.com>
6 * (C) Copyright 2007 Sergey Kubushyn <ksi@koi8.net>
7 * --------------------------------------------------------
9 * SPDX-License-Identifier: GPL-2.0+
11 * NOTE: This driver should be converted to driver model before June 2017.
12 * Please see doc/driver-model/i2c-howto.txt for instructions.
17 #include <asm/arch/hardware.h>
18 #include <asm/arch/i2c_defs.h>
20 #include "davinci_i2c.h"
22 #define CHECK_NACK() \
24 if (tmp & (I2C_TIMEOUT | I2C_STAT_NACK)) {\
25 REG(&(i2c_base->i2c_con)) = 0;\
30 static struct i2c_regs *davinci_get_base(struct i2c_adapter *adap);
32 static int wait_for_bus(struct i2c_adapter *adap)
34 struct i2c_regs *i2c_base = davinci_get_base(adap);
37 REG(&(i2c_base->i2c_stat)) = 0xffff;
39 for (timeout = 0; timeout < 10; timeout++) {
40 stat = REG(&(i2c_base->i2c_stat));
41 if (!((stat) & I2C_STAT_BB)) {
42 REG(&(i2c_base->i2c_stat)) = 0xffff;
46 REG(&(i2c_base->i2c_stat)) = stat;
50 REG(&(i2c_base->i2c_stat)) = 0xffff;
55 static int poll_i2c_irq(struct i2c_adapter *adap, int mask)
57 struct i2c_regs *i2c_base = davinci_get_base(adap);
60 for (timeout = 0; timeout < 10; timeout++) {
62 stat = REG(&(i2c_base->i2c_stat));
67 REG(&(i2c_base->i2c_stat)) = 0xffff;
68 return stat | I2C_TIMEOUT;
71 static void flush_rx(struct i2c_adapter *adap)
73 struct i2c_regs *i2c_base = davinci_get_base(adap);
76 if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_RRDY))
79 REG(&(i2c_base->i2c_drr));
80 REG(&(i2c_base->i2c_stat)) = I2C_STAT_RRDY;
85 static uint davinci_i2c_setspeed(struct i2c_adapter *adap, uint speed)
87 struct i2c_regs *i2c_base = davinci_get_base(adap);
92 div = (CONFIG_SYS_HZ_CLOCK / ((psc + 1) * speed)) - 10;
93 REG(&(i2c_base->i2c_psc)) = psc; /* 27MHz / (2 + 1) = 9MHz */
94 REG(&(i2c_base->i2c_scll)) = (div * 50) / 100; /* 50% Duty */
95 REG(&(i2c_base->i2c_sclh)) = div - REG(&(i2c_base->i2c_scll));
101 static void davinci_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
103 struct i2c_regs *i2c_base = davinci_get_base(adap);
105 if (REG(&(i2c_base->i2c_con)) & I2C_CON_EN) {
106 REG(&(i2c_base->i2c_con)) = 0;
110 davinci_i2c_setspeed(adap, speed);
112 REG(&(i2c_base->i2c_oa)) = slaveadd;
113 REG(&(i2c_base->i2c_cnt)) = 0;
115 /* Interrupts must be enabled or I2C module won't work */
116 REG(&(i2c_base->i2c_ie)) = I2C_IE_SCD_IE | I2C_IE_XRDY_IE |
117 I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | I2C_IE_NACK_IE;
119 /* Now enable I2C controller (get it out of reset) */
120 REG(&(i2c_base->i2c_con)) = I2C_CON_EN;
125 static int davinci_i2c_probe(struct i2c_adapter *adap, uint8_t chip)
127 struct i2c_regs *i2c_base = davinci_get_base(adap);
130 if (chip == REG(&(i2c_base->i2c_oa)))
133 REG(&(i2c_base->i2c_con)) = 0;
134 if (wait_for_bus(adap))
137 /* try to read one byte from current (or only) address */
138 REG(&(i2c_base->i2c_cnt)) = 1;
139 REG(&(i2c_base->i2c_sa)) = chip;
140 REG(&(i2c_base->i2c_con)) = (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
144 if (!(REG(&(i2c_base->i2c_stat)) & I2C_STAT_NACK)) {
147 REG(&(i2c_base->i2c_stat)) = 0xffff;
149 REG(&(i2c_base->i2c_stat)) = 0xffff;
150 REG(&(i2c_base->i2c_con)) |= I2C_CON_STP;
152 if (wait_for_bus(adap))
157 REG(&(i2c_base->i2c_stat)) = 0xffff;
158 REG(&(i2c_base->i2c_cnt)) = 0;
162 static int davinci_i2c_read(struct i2c_adapter *adap, uint8_t chip,
163 uint32_t addr, int alen, uint8_t *buf, int len)
165 struct i2c_regs *i2c_base = davinci_get_base(adap);
169 if ((alen < 0) || (alen > 2)) {
170 printf("%s(): bogus address length %x\n", __func__, alen);
174 if (wait_for_bus(adap))
178 /* Start address phase */
179 tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX;
180 REG(&(i2c_base->i2c_cnt)) = alen;
181 REG(&(i2c_base->i2c_sa)) = chip;
182 REG(&(i2c_base->i2c_con)) = tmp;
184 tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK);
190 /* Send address MSByte */
191 if (tmp & I2C_STAT_XRDY) {
192 REG(&(i2c_base->i2c_dxr)) = (addr >> 8) & 0xff;
194 REG(&(i2c_base->i2c_con)) = 0;
198 tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK);
201 /* No break, fall through */
203 /* Send address LSByte */
204 if (tmp & I2C_STAT_XRDY) {
205 REG(&(i2c_base->i2c_dxr)) = addr & 0xff;
207 REG(&(i2c_base->i2c_con)) = 0;
211 tmp = poll_i2c_irq(adap, I2C_STAT_XRDY |
212 I2C_STAT_NACK | I2C_STAT_ARDY);
216 if (!(tmp & I2C_STAT_ARDY)) {
217 REG(&(i2c_base->i2c_con)) = 0;
223 /* Address phase is over, now read 'len' bytes and stop */
224 tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP;
225 REG(&(i2c_base->i2c_cnt)) = len & 0xffff;
226 REG(&(i2c_base->i2c_sa)) = chip;
227 REG(&(i2c_base->i2c_con)) = tmp;
229 for (i = 0; i < len; i++) {
230 tmp = poll_i2c_irq(adap, I2C_STAT_RRDY | I2C_STAT_NACK |
235 if (tmp & I2C_STAT_RRDY) {
236 buf[i] = REG(&(i2c_base->i2c_drr));
238 REG(&(i2c_base->i2c_con)) = 0;
243 tmp = poll_i2c_irq(adap, I2C_STAT_SCD | I2C_STAT_NACK);
247 if (!(tmp & I2C_STAT_SCD)) {
248 REG(&(i2c_base->i2c_con)) = 0;
253 REG(&(i2c_base->i2c_stat)) = 0xffff;
254 REG(&(i2c_base->i2c_cnt)) = 0;
255 REG(&(i2c_base->i2c_con)) = 0;
260 static int davinci_i2c_write(struct i2c_adapter *adap, uint8_t chip,
261 uint32_t addr, int alen, uint8_t *buf, int len)
263 struct i2c_regs *i2c_base = davinci_get_base(adap);
267 if ((alen < 0) || (alen > 2)) {
268 printf("%s(): bogus address length %x\n", __func__, alen);
272 printf("%s(): bogus length %x\n", __func__, len);
276 if (wait_for_bus(adap))
279 /* Start address phase */
280 tmp = I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
281 I2C_CON_TRX | I2C_CON_STP;
282 REG(&(i2c_base->i2c_cnt)) = (alen == 0) ?
283 len & 0xffff : (len & 0xffff) + alen;
284 REG(&(i2c_base->i2c_sa)) = chip;
285 REG(&(i2c_base->i2c_con)) = tmp;
289 /* Send address MSByte */
290 tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK);
294 if (tmp & I2C_STAT_XRDY) {
295 REG(&(i2c_base->i2c_dxr)) = (addr >> 8) & 0xff;
297 REG(&(i2c_base->i2c_con)) = 0;
300 /* No break, fall through */
302 /* Send address LSByte */
303 tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK);
307 if (tmp & I2C_STAT_XRDY) {
308 REG(&(i2c_base->i2c_dxr)) = addr & 0xff;
310 REG(&(i2c_base->i2c_con)) = 0;
315 for (i = 0; i < len; i++) {
316 tmp = poll_i2c_irq(adap, I2C_STAT_XRDY | I2C_STAT_NACK);
320 if (tmp & I2C_STAT_XRDY)
321 REG(&(i2c_base->i2c_dxr)) = buf[i];
326 tmp = poll_i2c_irq(adap, I2C_STAT_SCD | I2C_STAT_NACK);
330 if (!(tmp & I2C_STAT_SCD)) {
331 REG(&(i2c_base->i2c_con)) = 0;
336 REG(&(i2c_base->i2c_stat)) = 0xffff;
337 REG(&(i2c_base->i2c_cnt)) = 0;
338 REG(&(i2c_base->i2c_con)) = 0;
343 static struct i2c_regs *davinci_get_base(struct i2c_adapter *adap)
345 switch (adap->hwadapnr) {
348 return (struct i2c_regs *)I2C2_BASE;
352 return (struct i2c_regs *)I2C1_BASE;
355 return (struct i2c_regs *)I2C_BASE;
358 printf("wrong hwadapnr: %d\n", adap->hwadapnr);
364 U_BOOT_I2C_ADAP_COMPLETE(davinci_0, davinci_i2c_init, davinci_i2c_probe,
365 davinci_i2c_read, davinci_i2c_write,
366 davinci_i2c_setspeed,
367 CONFIG_SYS_DAVINCI_I2C_SPEED,
368 CONFIG_SYS_DAVINCI_I2C_SLAVE,
372 U_BOOT_I2C_ADAP_COMPLETE(davinci_1, davinci_i2c_init, davinci_i2c_probe,
373 davinci_i2c_read, davinci_i2c_write,
374 davinci_i2c_setspeed,
375 CONFIG_SYS_DAVINCI_I2C_SPEED1,
376 CONFIG_SYS_DAVINCI_I2C_SLAVE1,
381 U_BOOT_I2C_ADAP_COMPLETE(davinci_2, davinci_i2c_init, davinci_i2c_probe,
382 davinci_i2c_read, davinci_i2c_write,
383 davinci_i2c_setspeed,
384 CONFIG_SYS_DAVINCI_I2C_SPEED2,
385 CONFIG_SYS_DAVINCI_I2C_SLAVE2,