3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
5 * SPDX-License-Identifier: GPL-2.0+
13 #include "designware_i2c.h"
15 struct dw_scl_sda_cfg {
24 /* BayTrail HCNT/LCNT/SDA hold time */
25 static struct dw_scl_sda_cfg byt_config = {
35 struct i2c_regs *regs;
36 struct dw_scl_sda_cfg *scl_sda_cfg;
39 #ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
40 static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
42 u32 ena = enable ? IC_ENABLE_0B : 0;
44 writel(ena, &i2c_base->ic_enable);
47 static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
49 u32 ena = enable ? IC_ENABLE_0B : 0;
53 writel(ena, &i2c_base->ic_enable);
54 if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
58 * Wait 10 times the signaling period of the highest I2C
59 * transfer supported by the driver (for 400KHz this is
60 * 25us) as described in the DesignWare I2C databook.
65 printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
70 * i2c_set_bus_speed - Set the i2c speed
71 * @speed: required i2c speed
75 static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base,
76 struct dw_scl_sda_cfg *scl_sda_cfg,
80 unsigned int hcnt, lcnt;
83 if (speed >= I2C_MAX_SPEED)
84 i2c_spd = IC_SPEED_MODE_MAX;
85 else if (speed >= I2C_FAST_SPEED)
86 i2c_spd = IC_SPEED_MODE_FAST;
88 i2c_spd = IC_SPEED_MODE_STANDARD;
90 /* to set speed cltr must be disabled */
91 dw_i2c_enable(i2c_base, false);
93 cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
96 #ifndef CONFIG_X86 /* No High-speed for BayTrail yet */
97 case IC_SPEED_MODE_MAX:
98 cntl |= IC_CON_SPD_SS;
100 hcnt = scl_sda_cfg->fs_hcnt;
101 lcnt = scl_sda_cfg->fs_lcnt;
103 hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
104 lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
106 writel(hcnt, &i2c_base->ic_hs_scl_hcnt);
107 writel(lcnt, &i2c_base->ic_hs_scl_lcnt);
111 case IC_SPEED_MODE_STANDARD:
112 cntl |= IC_CON_SPD_SS;
114 hcnt = scl_sda_cfg->ss_hcnt;
115 lcnt = scl_sda_cfg->ss_lcnt;
117 hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
118 lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
120 writel(hcnt, &i2c_base->ic_ss_scl_hcnt);
121 writel(lcnt, &i2c_base->ic_ss_scl_lcnt);
124 case IC_SPEED_MODE_FAST:
126 cntl |= IC_CON_SPD_FS;
128 hcnt = scl_sda_cfg->fs_hcnt;
129 lcnt = scl_sda_cfg->fs_lcnt;
131 hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
132 lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
134 writel(hcnt, &i2c_base->ic_fs_scl_hcnt);
135 writel(lcnt, &i2c_base->ic_fs_scl_lcnt);
139 writel(cntl, &i2c_base->ic_con);
141 /* Configure SDA Hold Time if required */
143 writel(scl_sda_cfg->sda_hold, &i2c_base->ic_sda_hold);
145 /* Enable back i2c now speed set */
146 dw_i2c_enable(i2c_base, true);
152 * i2c_setaddress - Sets the target slave address
153 * @i2c_addr: target i2c address
155 * Sets the target slave address.
157 static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
160 dw_i2c_enable(i2c_base, false);
162 writel(i2c_addr, &i2c_base->ic_tar);
165 dw_i2c_enable(i2c_base, true);
169 * i2c_flush_rxfifo - Flushes the i2c RX FIFO
171 * Flushes the i2c RX FIFO
173 static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
175 while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
176 readl(&i2c_base->ic_cmd_data);
180 * i2c_wait_for_bb - Waits for bus busy
184 static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
186 unsigned long start_time_bb = get_timer(0);
188 while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
189 !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
191 /* Evaluate timeout */
192 if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
199 static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
202 if (i2c_wait_for_bb(i2c_base))
205 i2c_setaddress(i2c_base, chip);
208 /* high byte address going out first */
209 writel((addr >> (alen * 8)) & 0xff,
210 &i2c_base->ic_cmd_data);
215 static int i2c_xfer_finish(struct i2c_regs *i2c_base)
217 ulong start_stop_det = get_timer(0);
220 if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
221 readl(&i2c_base->ic_clr_stop_det);
223 } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
228 if (i2c_wait_for_bb(i2c_base)) {
229 printf("Timed out waiting for bus\n");
233 i2c_flush_rxfifo(i2c_base);
239 * i2c_read - Read from i2c memory
240 * @chip: target i2c address
241 * @addr: address to read from
243 * @buffer: buffer for read data
244 * @len: no of bytes to be read
246 * Read from i2c memory.
248 static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
249 int alen, u8 *buffer, int len)
251 unsigned long start_time_rx;
252 unsigned int active = 0;
254 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
256 * EEPROM chips that implement "address overflow" are ones
257 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
258 * address and the extra bits end up in the "chip address"
259 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
260 * four 256 byte chips.
262 * Note that we consider the length of the address field to
263 * still be one byte because the extra address bits are
264 * hidden in the chip address.
266 dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
267 addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
269 debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
273 if (i2c_xfer_init(i2c_base, dev, addr, alen))
276 start_time_rx = get_timer(0);
280 * Avoid writing to ic_cmd_data multiple times
281 * in case this loop spins too quickly and the
282 * ic_status RFNE bit isn't set after the first
283 * write. Subsequent writes to ic_cmd_data can
284 * trigger spurious i2c transfer.
287 writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
289 writel(IC_CMD, &i2c_base->ic_cmd_data);
293 if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
294 *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
296 start_time_rx = get_timer(0);
298 } else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
303 return i2c_xfer_finish(i2c_base);
307 * i2c_write - Write to i2c memory
308 * @chip: target i2c address
309 * @addr: address to read from
311 * @buffer: buffer for read data
312 * @len: no of bytes to be read
314 * Write to i2c memory.
316 static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
317 int alen, u8 *buffer, int len)
320 unsigned long start_time_tx;
322 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
324 * EEPROM chips that implement "address overflow" are ones
325 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
326 * address and the extra bits end up in the "chip address"
327 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
328 * four 256 byte chips.
330 * Note that we consider the length of the address field to
331 * still be one byte because the extra address bits are
332 * hidden in the chip address.
334 dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
335 addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
337 debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
341 if (i2c_xfer_init(i2c_base, dev, addr, alen))
344 start_time_tx = get_timer(0);
346 if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
348 writel(*buffer | IC_STOP,
349 &i2c_base->ic_cmd_data);
351 writel(*buffer, &i2c_base->ic_cmd_data);
354 start_time_tx = get_timer(0);
356 } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
357 printf("Timed out. i2c write Failed\n");
362 return i2c_xfer_finish(i2c_base);
366 * __dw_i2c_init - Init function
367 * @speed: required i2c speed
368 * @slaveaddr: slave address for the device
370 * Initialization function.
372 static void __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
375 dw_i2c_enable(i2c_base, false);
377 writel(IC_CON_SD | IC_CON_RE | IC_CON_SPD_FS | IC_CON_MM,
379 writel(IC_RX_TL, &i2c_base->ic_rx_tl);
380 writel(IC_TX_TL, &i2c_base->ic_tx_tl);
381 writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
382 #ifndef CONFIG_DM_I2C
383 __dw_i2c_set_bus_speed(i2c_base, NULL, speed);
384 writel(slaveaddr, &i2c_base->ic_sar);
388 dw_i2c_enable(i2c_base, true);
391 #ifndef CONFIG_DM_I2C
393 * The legacy I2C functions. These need to get removed once
394 * all users of this driver are converted to DM.
396 static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
398 switch (adap->hwadapnr) {
399 #if CONFIG_SYS_I2C_BUS_MAX >= 4
401 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
403 #if CONFIG_SYS_I2C_BUS_MAX >= 3
405 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
407 #if CONFIG_SYS_I2C_BUS_MAX >= 2
409 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
412 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
414 printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
420 static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
424 return __dw_i2c_set_bus_speed(i2c_get_base(adap), NULL, speed);
427 static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
429 __dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
432 static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
433 int alen, u8 *buffer, int len)
435 return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
438 static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
439 int alen, u8 *buffer, int len)
441 return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
444 /* dw_i2c_probe - Probe the i2c chip */
445 static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
447 struct i2c_regs *i2c_base = i2c_get_base(adap);
452 * Try to read the first location of the chip.
454 ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
456 dw_i2c_init(adap, adap->speed, adap->slaveaddr);
461 U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
462 dw_i2c_write, dw_i2c_set_bus_speed,
463 CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
465 #if CONFIG_SYS_I2C_BUS_MAX >= 2
466 U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
467 dw_i2c_write, dw_i2c_set_bus_speed,
468 CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
471 #if CONFIG_SYS_I2C_BUS_MAX >= 3
472 U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
473 dw_i2c_write, dw_i2c_set_bus_speed,
474 CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
477 #if CONFIG_SYS_I2C_BUS_MAX >= 4
478 U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
479 dw_i2c_write, dw_i2c_set_bus_speed,
480 CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
483 #else /* CONFIG_DM_I2C */
484 /* The DM I2C functions */
486 static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
489 struct dw_i2c *i2c = dev_get_priv(bus);
492 debug("i2c_xfer: %d messages\n", nmsgs);
493 for (; nmsgs > 0; nmsgs--, msg++) {
494 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
495 if (msg->flags & I2C_M_RD) {
496 ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
499 ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
503 debug("i2c_write: error sending\n");
511 static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
513 struct dw_i2c *i2c = dev_get_priv(bus);
515 return __dw_i2c_set_bus_speed(i2c->regs, i2c->scl_sda_cfg, speed);
518 static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
521 struct dw_i2c *i2c = dev_get_priv(bus);
522 struct i2c_regs *i2c_base = i2c->regs;
526 /* Try to read the first location of the chip */
527 ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
529 __dw_i2c_init(i2c_base, 0, 0);
534 static int designware_i2c_probe(struct udevice *bus)
536 struct dw_i2c *priv = dev_get_priv(bus);
538 if (device_is_on_pci_bus(bus)) {
540 /* Save base address from PCI BAR */
541 priv->regs = (struct i2c_regs *)
542 dm_pci_map_bar(bus, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
544 /* Use BayTrail specific timing values */
545 priv->scl_sda_cfg = &byt_config;
549 priv->regs = (struct i2c_regs *)devfdt_get_addr_ptr(bus);
552 __dw_i2c_init(priv->regs, 0, 0);
557 static int designware_i2c_bind(struct udevice *dev)
559 static int num_cards;
562 /* Create a unique device name for PCI type devices */
563 if (device_is_on_pci_bus(dev)) {
566 * Setting req_seq in the driver is probably not recommended.
567 * But without a DT alias the number is not configured. And
568 * using this driver is impossible for PCIe I2C devices.
569 * This can be removed, once a better (correct) way for this
570 * is found and implemented.
572 dev->req_seq = num_cards;
573 sprintf(name, "i2c_designware#%u", num_cards++);
574 device_set_name(dev, name);
580 static const struct dm_i2c_ops designware_i2c_ops = {
581 .xfer = designware_i2c_xfer,
582 .probe_chip = designware_i2c_probe_chip,
583 .set_bus_speed = designware_i2c_set_bus_speed,
586 static const struct udevice_id designware_i2c_ids[] = {
587 { .compatible = "snps,designware-i2c" },
591 U_BOOT_DRIVER(i2c_designware) = {
592 .name = "i2c_designware",
594 .of_match = designware_i2c_ids,
595 .bind = designware_i2c_bind,
596 .probe = designware_i2c_probe,
597 .priv_auto_alloc_size = sizeof(struct dw_i2c),
598 .ops = &designware_i2c_ops,
602 static struct pci_device_id designware_pci_supported[] = {
603 /* Intel BayTrail has 7 I2C controller located on the PCI bus */
604 { PCI_VDEVICE(INTEL, 0x0f41) },
605 { PCI_VDEVICE(INTEL, 0x0f42) },
606 { PCI_VDEVICE(INTEL, 0x0f43) },
607 { PCI_VDEVICE(INTEL, 0x0f44) },
608 { PCI_VDEVICE(INTEL, 0x0f45) },
609 { PCI_VDEVICE(INTEL, 0x0f46) },
610 { PCI_VDEVICE(INTEL, 0x0f47) },
614 U_BOOT_PCI_DEVICE(i2c_designware, designware_pci_supported);
617 #endif /* CONFIG_DM_I2C */