3 * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/hardware.h>
11 #include "designware_i2c.h"
13 #ifdef CONFIG_I2C_MULTI_BUS
14 static unsigned int bus_initialized[CONFIG_SYS_I2C_BUS_MAX];
15 static unsigned int current_bus = 0;
18 static struct i2c_regs *i2c_regs_p =
19 (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
22 * set_speed - Set the i2c speed mode (standard, high, fast)
23 * @i2c_spd: required i2c speed mode
25 * Set the i2c speed mode (standard, high, fast)
27 static void set_speed(int i2c_spd)
30 unsigned int hcnt, lcnt;
33 /* to set speed cltr must be disabled */
34 enbl = readl(&i2c_regs_p->ic_enable);
35 enbl &= ~IC_ENABLE_0B;
36 writel(enbl, &i2c_regs_p->ic_enable);
38 cntl = (readl(&i2c_regs_p->ic_con) & (~IC_CON_SPD_MSK));
41 case IC_SPEED_MODE_MAX:
42 cntl |= IC_CON_SPD_HS;
43 hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
44 writel(hcnt, &i2c_regs_p->ic_hs_scl_hcnt);
45 lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
46 writel(lcnt, &i2c_regs_p->ic_hs_scl_lcnt);
49 case IC_SPEED_MODE_STANDARD:
50 cntl |= IC_CON_SPD_SS;
51 hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
52 writel(hcnt, &i2c_regs_p->ic_ss_scl_hcnt);
53 lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
54 writel(lcnt, &i2c_regs_p->ic_ss_scl_lcnt);
57 case IC_SPEED_MODE_FAST:
59 cntl |= IC_CON_SPD_FS;
60 hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
61 writel(hcnt, &i2c_regs_p->ic_fs_scl_hcnt);
62 lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
63 writel(lcnt, &i2c_regs_p->ic_fs_scl_lcnt);
67 writel(cntl, &i2c_regs_p->ic_con);
69 /* Enable back i2c now speed set */
71 writel(enbl, &i2c_regs_p->ic_enable);
75 * i2c_set_bus_speed - Set the i2c speed
76 * @speed: required i2c speed
80 int i2c_set_bus_speed(int speed)
82 if (speed >= I2C_MAX_SPEED)
83 set_speed(IC_SPEED_MODE_MAX);
84 else if (speed >= I2C_FAST_SPEED)
85 set_speed(IC_SPEED_MODE_FAST);
87 set_speed(IC_SPEED_MODE_STANDARD);
93 * i2c_get_bus_speed - Gets the i2c speed
97 int i2c_get_bus_speed(void)
101 cntl = (readl(&i2c_regs_p->ic_con) & IC_CON_SPD_MSK);
103 if (cntl == IC_CON_SPD_HS)
104 return I2C_MAX_SPEED;
105 else if (cntl == IC_CON_SPD_FS)
106 return I2C_FAST_SPEED;
107 else if (cntl == IC_CON_SPD_SS)
108 return I2C_STANDARD_SPEED;
114 * i2c_init - Init function
115 * @speed: required i2c speed
116 * @slaveadd: slave address for the device
118 * Initialization function.
120 void i2c_init(int speed, int slaveadd)
125 enbl = readl(&i2c_regs_p->ic_enable);
126 enbl &= ~IC_ENABLE_0B;
127 writel(enbl, &i2c_regs_p->ic_enable);
129 writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_regs_p->ic_con);
130 writel(IC_RX_TL, &i2c_regs_p->ic_rx_tl);
131 writel(IC_TX_TL, &i2c_regs_p->ic_tx_tl);
132 i2c_set_bus_speed(speed);
133 writel(IC_STOP_DET, &i2c_regs_p->ic_intr_mask);
134 writel(slaveadd, &i2c_regs_p->ic_sar);
137 enbl = readl(&i2c_regs_p->ic_enable);
138 enbl |= IC_ENABLE_0B;
139 writel(enbl, &i2c_regs_p->ic_enable);
141 #ifdef CONFIG_I2C_MULTI_BUS
142 bus_initialized[current_bus] = 1;
147 * i2c_setaddress - Sets the target slave address
148 * @i2c_addr: target i2c address
150 * Sets the target slave address.
152 static void i2c_setaddress(unsigned int i2c_addr)
157 enbl = readl(&i2c_regs_p->ic_enable);
158 enbl &= ~IC_ENABLE_0B;
159 writel(enbl, &i2c_regs_p->ic_enable);
161 writel(i2c_addr, &i2c_regs_p->ic_tar);
164 enbl = readl(&i2c_regs_p->ic_enable);
165 enbl |= IC_ENABLE_0B;
166 writel(enbl, &i2c_regs_p->ic_enable);
170 * i2c_flush_rxfifo - Flushes the i2c RX FIFO
172 * Flushes the i2c RX FIFO
174 static void i2c_flush_rxfifo(void)
176 while (readl(&i2c_regs_p->ic_status) & IC_STATUS_RFNE)
177 readl(&i2c_regs_p->ic_cmd_data);
181 * i2c_wait_for_bb - Waits for bus busy
185 static int i2c_wait_for_bb(void)
187 unsigned long start_time_bb = get_timer(0);
189 while ((readl(&i2c_regs_p->ic_status) & IC_STATUS_MA) ||
190 !(readl(&i2c_regs_p->ic_status) & IC_STATUS_TFE)) {
192 /* Evaluate timeout */
193 if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
200 /* check parameters for i2c_read and i2c_write */
201 static int check_params(uint addr, int alen, uchar *buffer, int len)
203 if (buffer == NULL) {
204 printf("Buffer is invalid\n");
209 printf("addr len %d not supported\n", alen);
213 if (addr + len > 256) {
214 printf("address out of range\n");
221 static int i2c_xfer_init(uchar chip, uint addr)
223 if (i2c_wait_for_bb())
226 i2c_setaddress(chip);
227 writel(addr, &i2c_regs_p->ic_cmd_data);
232 static int i2c_xfer_finish(void)
234 ulong start_stop_det = get_timer(0);
237 if ((readl(&i2c_regs_p->ic_raw_intr_stat) & IC_STOP_DET)) {
238 readl(&i2c_regs_p->ic_clr_stop_det);
240 } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
245 if (i2c_wait_for_bb()) {
246 printf("Timed out waiting for bus\n");
256 * i2c_read - Read from i2c memory
257 * @chip: target i2c address
258 * @addr: address to read from
260 * @buffer: buffer for read data
261 * @len: no of bytes to be read
263 * Read from i2c memory.
265 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
267 unsigned long start_time_rx;
269 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
271 * EEPROM chips that implement "address overflow" are ones
272 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
273 * address and the extra bits end up in the "chip address"
274 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
275 * four 256 byte chips.
277 * Note that we consider the length of the address field to
278 * still be one byte because the extra address bits are
279 * hidden in the chip address.
281 chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
282 addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
284 debug("%s: fix addr_overflow: chip %02x addr %02x\n", __func__, chip,
288 if (check_params(addr, alen, buffer, len))
291 if (i2c_xfer_init(chip, addr))
294 start_time_rx = get_timer(0);
297 writel(IC_CMD | IC_STOP, &i2c_regs_p->ic_cmd_data);
299 writel(IC_CMD, &i2c_regs_p->ic_cmd_data);
301 if (readl(&i2c_regs_p->ic_status) & IC_STATUS_RFNE) {
302 *buffer++ = (uchar)readl(&i2c_regs_p->ic_cmd_data);
304 start_time_rx = get_timer(0);
306 } else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
311 return i2c_xfer_finish();
315 * i2c_write - Write to i2c memory
316 * @chip: target i2c address
317 * @addr: address to read from
319 * @buffer: buffer for read data
320 * @len: no of bytes to be read
322 * Write to i2c memory.
324 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
327 unsigned long start_time_tx;
329 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
331 * EEPROM chips that implement "address overflow" are ones
332 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
333 * address and the extra bits end up in the "chip address"
334 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
335 * four 256 byte chips.
337 * Note that we consider the length of the address field to
338 * still be one byte because the extra address bits are
339 * hidden in the chip address.
341 chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
342 addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
344 debug("%s: fix addr_overflow: chip %02x addr %02x\n", __func__, chip,
348 if (check_params(addr, alen, buffer, len))
351 if (i2c_xfer_init(chip, addr))
354 start_time_tx = get_timer(0);
356 if (readl(&i2c_regs_p->ic_status) & IC_STATUS_TFNF) {
358 writel(*buffer | IC_STOP, &i2c_regs_p->ic_cmd_data);
360 writel(*buffer, &i2c_regs_p->ic_cmd_data);
362 start_time_tx = get_timer(0);
364 } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
365 printf("Timed out. i2c write Failed\n");
370 return i2c_xfer_finish();
374 * i2c_probe - Probe the i2c chip
376 int i2c_probe(uchar chip)
382 * Try to read the first location of the chip.
384 ret = i2c_read(chip, 0, 1, (uchar *)&tmp, 1);
386 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
391 #ifdef CONFIG_I2C_MULTI_BUS
392 int i2c_set_bus_num(unsigned int bus)
396 i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE;
398 #ifdef CONFIG_SYS_I2C_BASE1
400 i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE1;
403 #ifdef CONFIG_SYS_I2C_BASE2
405 i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE2;
408 #ifdef CONFIG_SYS_I2C_BASE3
410 i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE3;
413 #ifdef CONFIG_SYS_I2C_BASE4
415 i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE4;
418 #ifdef CONFIG_SYS_I2C_BASE5
420 i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE5;
423 #ifdef CONFIG_SYS_I2C_BASE6
425 i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE6;
428 #ifdef CONFIG_SYS_I2C_BASE7
430 i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE7;
433 #ifdef CONFIG_SYS_I2C_BASE8
435 i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE8;
438 #ifdef CONFIG_SYS_I2C_BASE9
440 i2c_regs_p = (void *)CONFIG_SYS_I2C_BASE9;
444 printf("Bad bus: %d\n", bus);
450 if (!bus_initialized[current_bus])
451 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
456 int i2c_get_bus_num(void)