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[u-boot] / drivers / i2c / designware_i2c.c
1 /*
2  * (C) Copyright 2009
3  * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
4  *
5  * SPDX-License-Identifier:     GPL-2.0+
6  */
7
8 #include <common.h>
9 #include <i2c.h>
10 #include <asm/io.h>
11 #include "designware_i2c.h"
12
13 static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
14 {
15         switch (adap->hwadapnr) {
16 #if CONFIG_SYS_I2C_BUS_MAX >= 4
17         case 3:
18                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
19 #endif
20 #if CONFIG_SYS_I2C_BUS_MAX >= 3
21         case 2:
22                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
23 #endif
24 #if CONFIG_SYS_I2C_BUS_MAX >= 2
25         case 1:
26                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
27 #endif
28         case 0:
29                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
30         default:
31                 printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
32         }
33
34         return NULL;
35 }
36
37 /*
38  * set_speed - Set the i2c speed mode (standard, high, fast)
39  * @i2c_spd:    required i2c speed mode
40  *
41  * Set the i2c speed mode (standard, high, fast)
42  */
43 static void set_speed(struct i2c_adapter *adap, int i2c_spd)
44 {
45         struct i2c_regs *i2c_base = i2c_get_base(adap);
46         unsigned int cntl;
47         unsigned int hcnt, lcnt;
48         unsigned int enbl;
49
50         /* to set speed cltr must be disabled */
51         enbl = readl(&i2c_base->ic_enable);
52         enbl &= ~IC_ENABLE_0B;
53         writel(enbl, &i2c_base->ic_enable);
54
55         cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
56
57         switch (i2c_spd) {
58         case IC_SPEED_MODE_MAX:
59                 cntl |= IC_CON_SPD_HS;
60                 hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
61                 writel(hcnt, &i2c_base->ic_hs_scl_hcnt);
62                 lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
63                 writel(lcnt, &i2c_base->ic_hs_scl_lcnt);
64                 break;
65
66         case IC_SPEED_MODE_STANDARD:
67                 cntl |= IC_CON_SPD_SS;
68                 hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
69                 writel(hcnt, &i2c_base->ic_ss_scl_hcnt);
70                 lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
71                 writel(lcnt, &i2c_base->ic_ss_scl_lcnt);
72                 break;
73
74         case IC_SPEED_MODE_FAST:
75         default:
76                 cntl |= IC_CON_SPD_FS;
77                 hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
78                 writel(hcnt, &i2c_base->ic_fs_scl_hcnt);
79                 lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
80                 writel(lcnt, &i2c_base->ic_fs_scl_lcnt);
81                 break;
82         }
83
84         writel(cntl, &i2c_base->ic_con);
85
86         /* Enable back i2c now speed set */
87         enbl |= IC_ENABLE_0B;
88         writel(enbl, &i2c_base->ic_enable);
89 }
90
91 /*
92  * i2c_set_bus_speed - Set the i2c speed
93  * @speed:      required i2c speed
94  *
95  * Set the i2c speed.
96  */
97 static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
98                                          unsigned int speed)
99 {
100         int i2c_spd;
101
102         if (speed >= I2C_MAX_SPEED)
103                 i2c_spd = IC_SPEED_MODE_MAX;
104         else if (speed >= I2C_FAST_SPEED)
105                 i2c_spd = IC_SPEED_MODE_FAST;
106         else
107                 i2c_spd = IC_SPEED_MODE_STANDARD;
108
109         set_speed(adap, i2c_spd);
110         adap->speed = speed;
111
112         return 0;
113 }
114
115 /*
116  * i2c_init - Init function
117  * @speed:      required i2c speed
118  * @slaveaddr:  slave address for the device
119  *
120  * Initialization function.
121  */
122 static void dw_i2c_init(struct i2c_adapter *adap, int speed,
123                         int slaveaddr)
124 {
125         struct i2c_regs *i2c_base = i2c_get_base(adap);
126         unsigned int enbl;
127
128         /* Disable i2c */
129         enbl = readl(&i2c_base->ic_enable);
130         enbl &= ~IC_ENABLE_0B;
131         writel(enbl, &i2c_base->ic_enable);
132
133         writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_base->ic_con);
134         writel(IC_RX_TL, &i2c_base->ic_rx_tl);
135         writel(IC_TX_TL, &i2c_base->ic_tx_tl);
136         dw_i2c_set_bus_speed(adap, speed);
137         writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
138         writel(slaveaddr, &i2c_base->ic_sar);
139
140         /* Enable i2c */
141         enbl = readl(&i2c_base->ic_enable);
142         enbl |= IC_ENABLE_0B;
143         writel(enbl, &i2c_base->ic_enable);
144 }
145
146 /*
147  * i2c_setaddress - Sets the target slave address
148  * @i2c_addr:   target i2c address
149  *
150  * Sets the target slave address.
151  */
152 static void i2c_setaddress(struct i2c_adapter *adap, unsigned int i2c_addr)
153 {
154         struct i2c_regs *i2c_base = i2c_get_base(adap);
155         unsigned int enbl;
156
157         /* Disable i2c */
158         enbl = readl(&i2c_base->ic_enable);
159         enbl &= ~IC_ENABLE_0B;
160         writel(enbl, &i2c_base->ic_enable);
161
162         writel(i2c_addr, &i2c_base->ic_tar);
163
164         /* Enable i2c */
165         enbl = readl(&i2c_base->ic_enable);
166         enbl |= IC_ENABLE_0B;
167         writel(enbl, &i2c_base->ic_enable);
168 }
169
170 /*
171  * i2c_flush_rxfifo - Flushes the i2c RX FIFO
172  *
173  * Flushes the i2c RX FIFO
174  */
175 static void i2c_flush_rxfifo(struct i2c_adapter *adap)
176 {
177         struct i2c_regs *i2c_base = i2c_get_base(adap);
178
179         while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
180                 readl(&i2c_base->ic_cmd_data);
181 }
182
183 /*
184  * i2c_wait_for_bb - Waits for bus busy
185  *
186  * Waits for bus busy
187  */
188 static int i2c_wait_for_bb(struct i2c_adapter *adap)
189 {
190         struct i2c_regs *i2c_base = i2c_get_base(adap);
191         unsigned long start_time_bb = get_timer(0);
192
193         while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
194                !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
195
196                 /* Evaluate timeout */
197                 if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
198                         return 1;
199         }
200
201         return 0;
202 }
203
204 static int i2c_xfer_init(struct i2c_adapter *adap, uchar chip, uint addr,
205                          int alen)
206 {
207         struct i2c_regs *i2c_base = i2c_get_base(adap);
208
209         if (i2c_wait_for_bb(adap))
210                 return 1;
211
212         i2c_setaddress(adap, chip);
213         while (alen) {
214                 alen--;
215                 /* high byte address going out first */
216                 writel((addr >> (alen * 8)) & 0xff,
217                        &i2c_base->ic_cmd_data);
218         }
219         return 0;
220 }
221
222 static int i2c_xfer_finish(struct i2c_adapter *adap)
223 {
224         struct i2c_regs *i2c_base = i2c_get_base(adap);
225         ulong start_stop_det = get_timer(0);
226
227         while (1) {
228                 if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
229                         readl(&i2c_base->ic_clr_stop_det);
230                         break;
231                 } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
232                         break;
233                 }
234         }
235
236         if (i2c_wait_for_bb(adap)) {
237                 printf("Timed out waiting for bus\n");
238                 return 1;
239         }
240
241         i2c_flush_rxfifo(adap);
242
243         return 0;
244 }
245
246 /*
247  * i2c_read - Read from i2c memory
248  * @chip:       target i2c address
249  * @addr:       address to read from
250  * @alen:
251  * @buffer:     buffer for read data
252  * @len:        no of bytes to be read
253  *
254  * Read from i2c memory.
255  */
256 static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
257                        int alen, u8 *buffer, int len)
258 {
259         struct i2c_regs *i2c_base = i2c_get_base(adap);
260         unsigned long start_time_rx;
261
262 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
263         /*
264          * EEPROM chips that implement "address overflow" are ones
265          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
266          * address and the extra bits end up in the "chip address"
267          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
268          * four 256 byte chips.
269          *
270          * Note that we consider the length of the address field to
271          * still be one byte because the extra address bits are
272          * hidden in the chip address.
273          */
274         dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
275         addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
276
277         debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
278               addr);
279 #endif
280
281         if (i2c_xfer_init(adap, dev, addr, alen))
282                 return 1;
283
284         start_time_rx = get_timer(0);
285         while (len) {
286                 if (len == 1)
287                         writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
288                 else
289                         writel(IC_CMD, &i2c_base->ic_cmd_data);
290
291                 if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
292                         *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
293                         len--;
294                         start_time_rx = get_timer(0);
295
296                 } else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
297                                 return 1;
298                 }
299         }
300
301         return i2c_xfer_finish(adap);
302 }
303
304 /*
305  * i2c_write - Write to i2c memory
306  * @chip:       target i2c address
307  * @addr:       address to read from
308  * @alen:
309  * @buffer:     buffer for read data
310  * @len:        no of bytes to be read
311  *
312  * Write to i2c memory.
313  */
314 static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
315                         int alen, u8 *buffer, int len)
316 {
317         struct i2c_regs *i2c_base = i2c_get_base(adap);
318         int nb = len;
319         unsigned long start_time_tx;
320
321 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
322         /*
323          * EEPROM chips that implement "address overflow" are ones
324          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
325          * address and the extra bits end up in the "chip address"
326          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
327          * four 256 byte chips.
328          *
329          * Note that we consider the length of the address field to
330          * still be one byte because the extra address bits are
331          * hidden in the chip address.
332          */
333         dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
334         addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
335
336         debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
337               addr);
338 #endif
339
340         if (i2c_xfer_init(adap, dev, addr, alen))
341                 return 1;
342
343         start_time_tx = get_timer(0);
344         while (len) {
345                 if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
346                         if (--len == 0) {
347                                 writel(*buffer | IC_STOP,
348                                        &i2c_base->ic_cmd_data);
349                         } else {
350                                 writel(*buffer, &i2c_base->ic_cmd_data);
351                         }
352                         buffer++;
353                         start_time_tx = get_timer(0);
354
355                 } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
356                                 printf("Timed out. i2c write Failed\n");
357                                 return 1;
358                 }
359         }
360
361         return i2c_xfer_finish(adap);
362 }
363
364 /*
365  * i2c_probe - Probe the i2c chip
366  */
367 static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
368 {
369         u32 tmp;
370         int ret;
371
372         /*
373          * Try to read the first location of the chip.
374          */
375         ret = dw_i2c_read(adap, dev, 0, 1, (uchar *)&tmp, 1);
376         if (ret)
377                 dw_i2c_init(adap, adap->speed, adap->slaveaddr);
378
379         return ret;
380 }
381
382 U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
383                          dw_i2c_write, dw_i2c_set_bus_speed,
384                          CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
385
386 #if CONFIG_SYS_I2C_BUS_MAX >= 2
387 U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
388                          dw_i2c_write, dw_i2c_set_bus_speed,
389                          CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
390 #endif
391
392 #if CONFIG_SYS_I2C_BUS_MAX >= 3
393 U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
394                          dw_i2c_write, dw_i2c_set_bus_speed,
395                          CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
396 #endif
397
398 #if CONFIG_SYS_I2C_BUS_MAX >= 4
399 U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
400                          dw_i2c_write, dw_i2c_set_bus_speed,
401                          CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
402 #endif