git.sur5r.net Git - u-boot/blob - drivers/i2c/designware_i2c.c

   1 /*
   2  * (C) Copyright 2009
   3  * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <i2c.h>
  10 #include <asm/io.h>
  11 #include "designware_i2c.h"
  12
  13 static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
  14 {
  15         switch (adap->hwadapnr) {
  16 #if CONFIG_SYS_I2C_BUS_MAX >= 4
  17         case 3:
  18                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
  19 #endif
  20 #if CONFIG_SYS_I2C_BUS_MAX >= 3
  21         case 2:
  22                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
  23 #endif
  24 #if CONFIG_SYS_I2C_BUS_MAX >= 2
  25         case 1:
  26                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
  27 #endif
  28         case 0:
  29                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
  30         default:
  31                 printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
  32         }
  33
  34         return NULL;
  35 }
  36
  37 static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
  38 {
  39         u32 ena = enable ? IC_ENABLE_0B : 0;
  40         int timeout = 100;
  41
  42         do {
  43                 writel(ena, &i2c_base->ic_enable);
  44                 if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
  45                         return;
  46
  47                 /*
  48                  * Wait 10 times the signaling period of the highest I2C
  49                  * transfer supported by the driver (for 400KHz this is
  50                  * 25us) as described in the DesignWare I2C databook.
  51                  */
  52                 udelay(25);
  53         } while (timeout--);
  54
  55         printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
  56 }
  57
  58 /*
  59  * set_speed - Set the i2c speed mode (standard, high, fast)
  60  * @i2c_spd:    required i2c speed mode
  61  *
  62  * Set the i2c speed mode (standard, high, fast)
  63  */
  64 static void set_speed(struct i2c_adapter *adap, int i2c_spd)
  65 {
  66         struct i2c_regs *i2c_base = i2c_get_base(adap);
  67         unsigned int cntl;
  68         unsigned int hcnt, lcnt;
  69
  70         /* to set speed cltr must be disabled */
  71         dw_i2c_enable(i2c_base, false);
  72
  73         cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
  74
  75         switch (i2c_spd) {
  76         case IC_SPEED_MODE_MAX:
  77                 cntl |= IC_CON_SPD_HS;
  78                 hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
  79                 writel(hcnt, &i2c_base->ic_hs_scl_hcnt);
  80                 lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
  81                 writel(lcnt, &i2c_base->ic_hs_scl_lcnt);
  82                 break;
  83
  84         case IC_SPEED_MODE_STANDARD:
  85                 cntl |= IC_CON_SPD_SS;
  86                 hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
  87                 writel(hcnt, &i2c_base->ic_ss_scl_hcnt);
  88                 lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
  89                 writel(lcnt, &i2c_base->ic_ss_scl_lcnt);
  90                 break;
  91
  92         case IC_SPEED_MODE_FAST:
  93         default:
  94                 cntl |= IC_CON_SPD_FS;
  95                 hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
  96                 writel(hcnt, &i2c_base->ic_fs_scl_hcnt);
  97                 lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
  98                 writel(lcnt, &i2c_base->ic_fs_scl_lcnt);
  99                 break;
 100         }
 101
 102         writel(cntl, &i2c_base->ic_con);
 103
 104         /* Enable back i2c now speed set */
 105         dw_i2c_enable(i2c_base, true);
 106 }
 107
 108 /*
 109  * i2c_set_bus_speed - Set the i2c speed
 110  * @speed:      required i2c speed
 111  *
 112  * Set the i2c speed.
 113  */
 114 static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
 115                                          unsigned int speed)
 116 {
 117         int i2c_spd;
 118
 119         if (speed >= I2C_MAX_SPEED)
 120                 i2c_spd = IC_SPEED_MODE_MAX;
 121         else if (speed >= I2C_FAST_SPEED)
 122                 i2c_spd = IC_SPEED_MODE_FAST;
 123         else
 124                 i2c_spd = IC_SPEED_MODE_STANDARD;
 125
 126         set_speed(adap, i2c_spd);
 127         adap->speed = speed;
 128
 129         return 0;
 130 }
 131
 132 /*
 133  * i2c_init - Init function
 134  * @speed:      required i2c speed
 135  * @slaveaddr:  slave address for the device
 136  *
 137  * Initialization function.
 138  */
 139 static void dw_i2c_init(struct i2c_adapter *adap, int speed,
 140                         int slaveaddr)
 141 {
 142         struct i2c_regs *i2c_base = i2c_get_base(adap);
 143
 144         /* Disable i2c */
 145         dw_i2c_enable(i2c_base, false);
 146
 147         writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_base->ic_con);
 148         writel(IC_RX_TL, &i2c_base->ic_rx_tl);
 149         writel(IC_TX_TL, &i2c_base->ic_tx_tl);
 150         dw_i2c_set_bus_speed(adap, speed);
 151         writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
 152         writel(slaveaddr, &i2c_base->ic_sar);
 153
 154         /* Enable i2c */
 155         dw_i2c_enable(i2c_base, true);
 156 }
 157
 158 /*
 159  * i2c_setaddress - Sets the target slave address
 160  * @i2c_addr:   target i2c address
 161  *
 162  * Sets the target slave address.
 163  */
 164 static void i2c_setaddress(struct i2c_adapter *adap, unsigned int i2c_addr)
 165 {
 166         struct i2c_regs *i2c_base = i2c_get_base(adap);
 167
 168         /* Disable i2c */
 169         dw_i2c_enable(i2c_base, false);
 170
 171         writel(i2c_addr, &i2c_base->ic_tar);
 172
 173         /* Enable i2c */
 174         dw_i2c_enable(i2c_base, true);
 175 }
 176
 177 /*
 178  * i2c_flush_rxfifo - Flushes the i2c RX FIFO
 179  *
 180  * Flushes the i2c RX FIFO
 181  */
 182 static void i2c_flush_rxfifo(struct i2c_adapter *adap)
 183 {
 184         struct i2c_regs *i2c_base = i2c_get_base(adap);
 185
 186         while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
 187                 readl(&i2c_base->ic_cmd_data);
 188 }
 189
 190 /*
 191  * i2c_wait_for_bb - Waits for bus busy
 192  *
 193  * Waits for bus busy
 194  */
 195 static int i2c_wait_for_bb(struct i2c_adapter *adap)
 196 {
 197         struct i2c_regs *i2c_base = i2c_get_base(adap);
 198         unsigned long start_time_bb = get_timer(0);
 199
 200         while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
 201                !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
 202
 203                 /* Evaluate timeout */
 204                 if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
 205                         return 1;
 206         }
 207
 208         return 0;
 209 }
 210
 211 static int i2c_xfer_init(struct i2c_adapter *adap, uchar chip, uint addr,
 212                          int alen)
 213 {
 214         struct i2c_regs *i2c_base = i2c_get_base(adap);
 215
 216         if (i2c_wait_for_bb(adap))
 217                 return 1;
 218
 219         i2c_setaddress(adap, chip);
 220         while (alen) {
 221                 alen--;
 222                 /* high byte address going out first */
 223                 writel((addr >> (alen * 8)) & 0xff,
 224                        &i2c_base->ic_cmd_data);
 225         }
 226         return 0;
 227 }
 228
 229 static int i2c_xfer_finish(struct i2c_adapter *adap)
 230 {
 231         struct i2c_regs *i2c_base = i2c_get_base(adap);
 232         ulong start_stop_det = get_timer(0);
 233
 234         while (1) {
 235                 if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
 236                         readl(&i2c_base->ic_clr_stop_det);
 237                         break;
 238                 } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
 239                         break;
 240                 }
 241         }
 242
 243         if (i2c_wait_for_bb(adap)) {
 244                 printf("Timed out waiting for bus\n");
 245                 return 1;
 246         }
 247
 248         i2c_flush_rxfifo(adap);
 249
 250         return 0;
 251 }
 252
 253 /*
 254  * i2c_read - Read from i2c memory
 255  * @chip:       target i2c address
 256  * @addr:       address to read from
 257  * @alen:
 258  * @buffer:     buffer for read data
 259  * @len:        no of bytes to be read
 260  *
 261  * Read from i2c memory.
 262  */
 263 static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
 264                        int alen, u8 *buffer, int len)
 265 {
 266         struct i2c_regs *i2c_base = i2c_get_base(adap);
 267         unsigned long start_time_rx;
 268
 269 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 270         /*
 271          * EEPROM chips that implement "address overflow" are ones
 272          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 273          * address and the extra bits end up in the "chip address"
 274          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 275          * four 256 byte chips.
 276          *
 277          * Note that we consider the length of the address field to
 278          * still be one byte because the extra address bits are
 279          * hidden in the chip address.
 280          */
 281         dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 282         addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
 283
 284         debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
 285               addr);
 286 #endif
 287
 288         if (i2c_xfer_init(adap, dev, addr, alen))
 289                 return 1;
 290
 291         start_time_rx = get_timer(0);
 292         while (len) {
 293                 if (len == 1)
 294                         writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
 295                 else
 296                         writel(IC_CMD, &i2c_base->ic_cmd_data);
 297
 298                 if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
 299                         *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
 300                         len--;
 301                         start_time_rx = get_timer(0);
 302
 303                 } else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
 304                                 return 1;
 305                 }
 306         }
 307
 308         return i2c_xfer_finish(adap);
 309 }
 310
 311 /*
 312  * i2c_write - Write to i2c memory
 313  * @chip:       target i2c address
 314  * @addr:       address to read from
 315  * @alen:
 316  * @buffer:     buffer for read data
 317  * @len:        no of bytes to be read
 318  *
 319  * Write to i2c memory.
 320  */
 321 static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
 322                         int alen, u8 *buffer, int len)
 323 {
 324         struct i2c_regs *i2c_base = i2c_get_base(adap);
 325         int nb = len;
 326         unsigned long start_time_tx;
 327
 328 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 329         /*
 330          * EEPROM chips that implement "address overflow" are ones
 331          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 332          * address and the extra bits end up in the "chip address"
 333          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 334          * four 256 byte chips.
 335          *
 336          * Note that we consider the length of the address field to
 337          * still be one byte because the extra address bits are
 338          * hidden in the chip address.
 339          */
 340         dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 341         addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
 342
 343         debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
 344               addr);
 345 #endif
 346
 347         if (i2c_xfer_init(adap, dev, addr, alen))
 348                 return 1;
 349
 350         start_time_tx = get_timer(0);
 351         while (len) {
 352                 if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
 353                         if (--len == 0) {
 354                                 writel(*buffer | IC_STOP,
 355                                        &i2c_base->ic_cmd_data);
 356                         } else {
 357                                 writel(*buffer, &i2c_base->ic_cmd_data);
 358                         }
 359                         buffer++;
 360                         start_time_tx = get_timer(0);
 361
 362                 } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
 363                                 printf("Timed out. i2c write Failed\n");
 364                                 return 1;
 365                 }
 366         }
 367
 368         return i2c_xfer_finish(adap);
 369 }
 370
 371 /*
 372  * i2c_probe - Probe the i2c chip
 373  */
 374 static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
 375 {
 376         u32 tmp;
 377         int ret;
 378
 379         /*
 380          * Try to read the first location of the chip.
 381          */
 382         ret = dw_i2c_read(adap, dev, 0, 1, (uchar *)&tmp, 1);
 383         if (ret)
 384                 dw_i2c_init(adap, adap->speed, adap->slaveaddr);
 385
 386         return ret;
 387 }
 388
 389 U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 390                          dw_i2c_write, dw_i2c_set_bus_speed,
 391                          CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
 392
 393 #if CONFIG_SYS_I2C_BUS_MAX >= 2
 394 U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 395                          dw_i2c_write, dw_i2c_set_bus_speed,
 396                          CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
 397 #endif
 398
 399 #if CONFIG_SYS_I2C_BUS_MAX >= 3
 400 U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 401                          dw_i2c_write, dw_i2c_set_bus_speed,
 402                          CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
 403 #endif
 404
 405 #if CONFIG_SYS_I2C_BUS_MAX >= 4
 406 U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 407                          dw_i2c_write, dw_i2c_set_bus_speed,
 408                          CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
 409 #endif