git.sur5r.net Git - u-boot/blob - drivers/i2c/designware_i2c.c

   1 /*
   2  * (C) Copyright 2009
   3  * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <dm.h>
  10 #include <i2c.h>
  11 #include <pci.h>
  12 #include <asm/io.h>
  13 #include "designware_i2c.h"
  14
  15 struct dw_scl_sda_cfg {
  16         u32 ss_hcnt;
  17         u32 fs_hcnt;
  18         u32 ss_lcnt;
  19         u32 fs_lcnt;
  20         u32 sda_hold;
  21 };
  22
  23 #ifdef CONFIG_X86
  24 /* BayTrail HCNT/LCNT/SDA hold time */
  25 static struct dw_scl_sda_cfg byt_config = {
  26         .ss_hcnt = 0x200,
  27         .fs_hcnt = 0x55,
  28         .ss_lcnt = 0x200,
  29         .fs_lcnt = 0x99,
  30         .sda_hold = 0x6,
  31 };
  32 #endif
  33
  34 struct dw_i2c {
  35         struct i2c_regs *regs;
  36         struct dw_scl_sda_cfg *scl_sda_cfg;
  37 };
  38
  39 #ifdef CONFIG_SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
  40 static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
  41 {
  42         u32 ena = enable ? IC_ENABLE_0B : 0;
  43
  44         writel(ena, &i2c_base->ic_enable);
  45 }
  46 #else
  47 static void dw_i2c_enable(struct i2c_regs *i2c_base, bool enable)
  48 {
  49         u32 ena = enable ? IC_ENABLE_0B : 0;
  50         int timeout = 100;
  51
  52         do {
  53                 writel(ena, &i2c_base->ic_enable);
  54                 if ((readl(&i2c_base->ic_enable_status) & IC_ENABLE_0B) == ena)
  55                         return;
  56
  57                 /*
  58                  * Wait 10 times the signaling period of the highest I2C
  59                  * transfer supported by the driver (for 400KHz this is
  60                  * 25us) as described in the DesignWare I2C databook.
  61                  */
  62                 udelay(25);
  63         } while (timeout--);
  64
  65         printf("timeout in %sabling I2C adapter\n", enable ? "en" : "dis");
  66 }
  67 #endif
  68
  69 /*
  70  * i2c_set_bus_speed - Set the i2c speed
  71  * @speed:      required i2c speed
  72  *
  73  * Set the i2c speed.
  74  */
  75 static unsigned int __dw_i2c_set_bus_speed(struct i2c_regs *i2c_base,
  76                                            struct dw_scl_sda_cfg *scl_sda_cfg,
  77                                            unsigned int speed)
  78 {
  79         unsigned int cntl;
  80         unsigned int hcnt, lcnt;
  81         int i2c_spd;
  82
  83         if (speed >= I2C_MAX_SPEED)
  84                 i2c_spd = IC_SPEED_MODE_MAX;
  85         else if (speed >= I2C_FAST_SPEED)
  86                 i2c_spd = IC_SPEED_MODE_FAST;
  87         else
  88                 i2c_spd = IC_SPEED_MODE_STANDARD;
  89
  90         /* to set speed cltr must be disabled */
  91         dw_i2c_enable(i2c_base, false);
  92
  93         cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
  94
  95         switch (i2c_spd) {
  96 #ifndef CONFIG_X86 /* No High-speed for BayTrail yet */
  97         case IC_SPEED_MODE_MAX:
  98                 cntl |= IC_CON_SPD_SS;
  99                 if (scl_sda_cfg) {
 100                         hcnt = scl_sda_cfg->fs_hcnt;
 101                         lcnt = scl_sda_cfg->fs_lcnt;
 102                 } else {
 103                         hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
 104                         lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
 105                 }
 106                 writel(hcnt, &i2c_base->ic_hs_scl_hcnt);
 107                 writel(lcnt, &i2c_base->ic_hs_scl_lcnt);
 108                 break;
 109 #endif
 110
 111         case IC_SPEED_MODE_STANDARD:
 112                 cntl |= IC_CON_SPD_SS;
 113                 if (scl_sda_cfg) {
 114                         hcnt = scl_sda_cfg->ss_hcnt;
 115                         lcnt = scl_sda_cfg->ss_lcnt;
 116                 } else {
 117                         hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
 118                         lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
 119                 }
 120                 writel(hcnt, &i2c_base->ic_ss_scl_hcnt);
 121                 writel(lcnt, &i2c_base->ic_ss_scl_lcnt);
 122                 break;
 123
 124         case IC_SPEED_MODE_FAST:
 125         default:
 126                 cntl |= IC_CON_SPD_FS;
 127                 if (scl_sda_cfg) {
 128                         hcnt = scl_sda_cfg->fs_hcnt;
 129                         lcnt = scl_sda_cfg->fs_lcnt;
 130                 } else {
 131                         hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
 132                         lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
 133                 }
 134                 writel(hcnt, &i2c_base->ic_fs_scl_hcnt);
 135                 writel(lcnt, &i2c_base->ic_fs_scl_lcnt);
 136                 break;
 137         }
 138
 139         writel(cntl, &i2c_base->ic_con);
 140
 141         /* Configure SDA Hold Time if required */
 142         if (scl_sda_cfg)
 143                 writel(scl_sda_cfg->sda_hold, &i2c_base->ic_sda_hold);
 144
 145         /* Enable back i2c now speed set */
 146         dw_i2c_enable(i2c_base, true);
 147
 148         return 0;
 149 }
 150
 151 /*
 152  * i2c_setaddress - Sets the target slave address
 153  * @i2c_addr:   target i2c address
 154  *
 155  * Sets the target slave address.
 156  */
 157 static void i2c_setaddress(struct i2c_regs *i2c_base, unsigned int i2c_addr)
 158 {
 159         /* Disable i2c */
 160         dw_i2c_enable(i2c_base, false);
 161
 162         writel(i2c_addr, &i2c_base->ic_tar);
 163
 164         /* Enable i2c */
 165         dw_i2c_enable(i2c_base, true);
 166 }
 167
 168 /*
 169  * i2c_flush_rxfifo - Flushes the i2c RX FIFO
 170  *
 171  * Flushes the i2c RX FIFO
 172  */
 173 static void i2c_flush_rxfifo(struct i2c_regs *i2c_base)
 174 {
 175         while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
 176                 readl(&i2c_base->ic_cmd_data);
 177 }
 178
 179 /*
 180  * i2c_wait_for_bb - Waits for bus busy
 181  *
 182  * Waits for bus busy
 183  */
 184 static int i2c_wait_for_bb(struct i2c_regs *i2c_base)
 185 {
 186         unsigned long start_time_bb = get_timer(0);
 187
 188         while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
 189                !(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
 190
 191                 /* Evaluate timeout */
 192                 if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
 193                         return 1;
 194         }
 195
 196         return 0;
 197 }
 198
 199 static int i2c_xfer_init(struct i2c_regs *i2c_base, uchar chip, uint addr,
 200                          int alen)
 201 {
 202         if (i2c_wait_for_bb(i2c_base))
 203                 return 1;
 204
 205         i2c_setaddress(i2c_base, chip);
 206         while (alen) {
 207                 alen--;
 208                 /* high byte address going out first */
 209                 writel((addr >> (alen * 8)) & 0xff,
 210                        &i2c_base->ic_cmd_data);
 211         }
 212         return 0;
 213 }
 214
 215 static int i2c_xfer_finish(struct i2c_regs *i2c_base)
 216 {
 217         ulong start_stop_det = get_timer(0);
 218
 219         while (1) {
 220                 if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
 221                         readl(&i2c_base->ic_clr_stop_det);
 222                         break;
 223                 } else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
 224                         break;
 225                 }
 226         }
 227
 228         if (i2c_wait_for_bb(i2c_base)) {
 229                 printf("Timed out waiting for bus\n");
 230                 return 1;
 231         }
 232
 233         i2c_flush_rxfifo(i2c_base);
 234
 235         return 0;
 236 }
 237
 238 /*
 239  * i2c_read - Read from i2c memory
 240  * @chip:       target i2c address
 241  * @addr:       address to read from
 242  * @alen:
 243  * @buffer:     buffer for read data
 244  * @len:        no of bytes to be read
 245  *
 246  * Read from i2c memory.
 247  */
 248 static int __dw_i2c_read(struct i2c_regs *i2c_base, u8 dev, uint addr,
 249                          int alen, u8 *buffer, int len)
 250 {
 251         unsigned long start_time_rx;
 252
 253 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 254         /*
 255          * EEPROM chips that implement "address overflow" are ones
 256          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 257          * address and the extra bits end up in the "chip address"
 258          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 259          * four 256 byte chips.
 260          *
 261          * Note that we consider the length of the address field to
 262          * still be one byte because the extra address bits are
 263          * hidden in the chip address.
 264          */
 265         dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 266         addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
 267
 268         debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
 269               addr);
 270 #endif
 271
 272         if (i2c_xfer_init(i2c_base, dev, addr, alen))
 273                 return 1;
 274
 275         start_time_rx = get_timer(0);
 276         while (len) {
 277                 if (len == 1)
 278                         writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
 279                 else
 280                         writel(IC_CMD, &i2c_base->ic_cmd_data);
 281
 282                 if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
 283                         *buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
 284                         len--;
 285                         start_time_rx = get_timer(0);
 286
 287                 } else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
 288                                 return 1;
 289                 }
 290         }
 291
 292         return i2c_xfer_finish(i2c_base);
 293 }
 294
 295 /*
 296  * i2c_write - Write to i2c memory
 297  * @chip:       target i2c address
 298  * @addr:       address to read from
 299  * @alen:
 300  * @buffer:     buffer for read data
 301  * @len:        no of bytes to be read
 302  *
 303  * Write to i2c memory.
 304  */
 305 static int __dw_i2c_write(struct i2c_regs *i2c_base, u8 dev, uint addr,
 306                           int alen, u8 *buffer, int len)
 307 {
 308         int nb = len;
 309         unsigned long start_time_tx;
 310
 311 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 312         /*
 313          * EEPROM chips that implement "address overflow" are ones
 314          * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
 315          * address and the extra bits end up in the "chip address"
 316          * bit slots. This makes a 24WC08 (1Kbyte) chip look like
 317          * four 256 byte chips.
 318          *
 319          * Note that we consider the length of the address field to
 320          * still be one byte because the extra address bits are
 321          * hidden in the chip address.
 322          */
 323         dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 324         addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
 325
 326         debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
 327               addr);
 328 #endif
 329
 330         if (i2c_xfer_init(i2c_base, dev, addr, alen))
 331                 return 1;
 332
 333         start_time_tx = get_timer(0);
 334         while (len) {
 335                 if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
 336                         if (--len == 0) {
 337                                 writel(*buffer | IC_STOP,
 338                                        &i2c_base->ic_cmd_data);
 339                         } else {
 340                                 writel(*buffer, &i2c_base->ic_cmd_data);
 341                         }
 342                         buffer++;
 343                         start_time_tx = get_timer(0);
 344
 345                 } else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
 346                                 printf("Timed out. i2c write Failed\n");
 347                                 return 1;
 348                 }
 349         }
 350
 351         return i2c_xfer_finish(i2c_base);
 352 }
 353
 354 /*
 355  * __dw_i2c_init - Init function
 356  * @speed:      required i2c speed
 357  * @slaveaddr:  slave address for the device
 358  *
 359  * Initialization function.
 360  */
 361 static void __dw_i2c_init(struct i2c_regs *i2c_base, int speed, int slaveaddr)
 362 {
 363         /* Disable i2c */
 364         dw_i2c_enable(i2c_base, false);
 365
 366         writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_base->ic_con);
 367         writel(IC_RX_TL, &i2c_base->ic_rx_tl);
 368         writel(IC_TX_TL, &i2c_base->ic_tx_tl);
 369         writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
 370 #ifndef CONFIG_DM_I2C
 371         __dw_i2c_set_bus_speed(i2c_base, NULL, speed);
 372         writel(slaveaddr, &i2c_base->ic_sar);
 373 #endif
 374
 375         /* Enable i2c */
 376         dw_i2c_enable(i2c_base, true);
 377 }
 378
 379 #ifndef CONFIG_DM_I2C
 380 /*
 381  * The legacy I2C functions. These need to get removed once
 382  * all users of this driver are converted to DM.
 383  */
 384 static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
 385 {
 386         switch (adap->hwadapnr) {
 387 #if CONFIG_SYS_I2C_BUS_MAX >= 4
 388         case 3:
 389                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
 390 #endif
 391 #if CONFIG_SYS_I2C_BUS_MAX >= 3
 392         case 2:
 393                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
 394 #endif
 395 #if CONFIG_SYS_I2C_BUS_MAX >= 2
 396         case 1:
 397                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
 398 #endif
 399         case 0:
 400                 return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
 401         default:
 402                 printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
 403         }
 404
 405         return NULL;
 406 }
 407
 408 static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
 409                                          unsigned int speed)
 410 {
 411         adap->speed = speed;
 412         return __dw_i2c_set_bus_speed(i2c_get_base(adap), NULL, speed);
 413 }
 414
 415 static void dw_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr)
 416 {
 417         __dw_i2c_init(i2c_get_base(adap), speed, slaveaddr);
 418 }
 419
 420 static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
 421                        int alen, u8 *buffer, int len)
 422 {
 423         return __dw_i2c_read(i2c_get_base(adap), dev, addr, alen, buffer, len);
 424 }
 425
 426 static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
 427                         int alen, u8 *buffer, int len)
 428 {
 429         return __dw_i2c_write(i2c_get_base(adap), dev, addr, alen, buffer, len);
 430 }
 431
 432 /* dw_i2c_probe - Probe the i2c chip */
 433 static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
 434 {
 435         struct i2c_regs *i2c_base = i2c_get_base(adap);
 436         u32 tmp;
 437         int ret;
 438
 439         /*
 440          * Try to read the first location of the chip.
 441          */
 442         ret = __dw_i2c_read(i2c_base, dev, 0, 1, (uchar *)&tmp, 1);
 443         if (ret)
 444                 dw_i2c_init(adap, adap->speed, adap->slaveaddr);
 445
 446         return ret;
 447 }
 448
 449 U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 450                          dw_i2c_write, dw_i2c_set_bus_speed,
 451                          CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
 452
 453 #if CONFIG_SYS_I2C_BUS_MAX >= 2
 454 U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 455                          dw_i2c_write, dw_i2c_set_bus_speed,
 456                          CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
 457 #endif
 458
 459 #if CONFIG_SYS_I2C_BUS_MAX >= 3
 460 U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 461                          dw_i2c_write, dw_i2c_set_bus_speed,
 462                          CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
 463 #endif
 464
 465 #if CONFIG_SYS_I2C_BUS_MAX >= 4
 466 U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
 467                          dw_i2c_write, dw_i2c_set_bus_speed,
 468                          CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
 469 #endif
 470
 471 #else /* CONFIG_DM_I2C */
 472 /* The DM I2C functions */
 473
 474 static int designware_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
 475                                int nmsgs)
 476 {
 477         struct dw_i2c *i2c = dev_get_priv(bus);
 478         int ret;
 479
 480         debug("i2c_xfer: %d messages\n", nmsgs);
 481         for (; nmsgs > 0; nmsgs--, msg++) {
 482                 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
 483                 if (msg->flags & I2C_M_RD) {
 484                         ret = __dw_i2c_read(i2c->regs, msg->addr, 0, 0,
 485                                             msg->buf, msg->len);
 486                 } else {
 487                         ret = __dw_i2c_write(i2c->regs, msg->addr, 0, 0,
 488                                              msg->buf, msg->len);
 489                 }
 490                 if (ret) {
 491                         debug("i2c_write: error sending\n");
 492                         return -EREMOTEIO;
 493                 }
 494         }
 495
 496         return 0;
 497 }
 498
 499 static int designware_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
 500 {
 501         struct dw_i2c *i2c = dev_get_priv(bus);
 502
 503         return __dw_i2c_set_bus_speed(i2c->regs, i2c->scl_sda_cfg, speed);
 504 }
 505
 506 static int designware_i2c_probe_chip(struct udevice *bus, uint chip_addr,
 507                                      uint chip_flags)
 508 {
 509         struct dw_i2c *i2c = dev_get_priv(bus);
 510         struct i2c_regs *i2c_base = i2c->regs;
 511         u32 tmp;
 512         int ret;
 513
 514         /* Try to read the first location of the chip */
 515         ret = __dw_i2c_read(i2c_base, chip_addr, 0, 1, (uchar *)&tmp, 1);
 516         if (ret)
 517                 __dw_i2c_init(i2c_base, 0, 0);
 518
 519         return ret;
 520 }
 521
 522 static int designware_i2c_probe(struct udevice *bus)
 523 {
 524         struct dw_i2c *priv = dev_get_priv(bus);
 525
 526         if (device_is_on_pci_bus(bus)) {
 527 #ifdef CONFIG_DM_PCI
 528                 /* Save base address from PCI BAR */
 529                 priv->regs = (struct i2c_regs *)
 530                         dm_pci_map_bar(bus, PCI_BASE_ADDRESS_0, PCI_REGION_MEM);
 531 #ifdef CONFIG_X86
 532                 /* Use BayTrail specific timing values */
 533                 priv->scl_sda_cfg = &byt_config;
 534 #endif
 535 #endif
 536         } else {
 537                 priv->regs = (struct i2c_regs *)dev_get_addr_ptr(bus);
 538         }
 539
 540         __dw_i2c_init(priv->regs, 0, 0);
 541
 542         return 0;
 543 }
 544
 545 static int designware_i2c_bind(struct udevice *dev)
 546 {
 547         static int num_cards;
 548         char name[20];
 549
 550         /* Create a unique device name for PCI type devices */
 551         if (device_is_on_pci_bus(dev)) {
 552                 /*
 553                  * ToDo:
 554                  * Setting req_seq in the driver is probably not recommended.
 555                  * But without a DT alias the number is not configured. And
 556                  * using this driver is impossible for PCIe I2C devices.
 557                  * This can be removed, once a better (correct) way for this
 558                  * is found and implemented.
 559                  */
 560                 dev->req_seq = num_cards;
 561                 sprintf(name, "i2c_designware#%u", num_cards++);
 562                 device_set_name(dev, name);
 563         }
 564
 565         return 0;
 566 }
 567
 568 static const struct dm_i2c_ops designware_i2c_ops = {
 569         .xfer           = designware_i2c_xfer,
 570         .probe_chip     = designware_i2c_probe_chip,
 571         .set_bus_speed  = designware_i2c_set_bus_speed,
 572 };
 573
 574 static const struct udevice_id designware_i2c_ids[] = {
 575         { .compatible = "snps,designware-i2c" },
 576         { }
 577 };
 578
 579 U_BOOT_DRIVER(i2c_designware) = {
 580         .name   = "i2c_designware",
 581         .id     = UCLASS_I2C,
 582         .of_match = designware_i2c_ids,
 583         .bind   = designware_i2c_bind,
 584         .probe  = designware_i2c_probe,
 585         .priv_auto_alloc_size = sizeof(struct dw_i2c),
 586         .ops    = &designware_i2c_ops,
 587 };
 588
 589 #ifdef CONFIG_X86
 590 static struct pci_device_id designware_pci_supported[] = {
 591         /* Intel BayTrail has 7 I2C controller located on the PCI bus */
 592         { PCI_VDEVICE(INTEL, 0x0f41) },
 593         { PCI_VDEVICE(INTEL, 0x0f42) },
 594         { PCI_VDEVICE(INTEL, 0x0f43) },
 595         { PCI_VDEVICE(INTEL, 0x0f44) },
 596         { PCI_VDEVICE(INTEL, 0x0f45) },
 597         { PCI_VDEVICE(INTEL, 0x0f46) },
 598         { PCI_VDEVICE(INTEL, 0x0f47) },
 599         {},
 600 };
 601
 602 U_BOOT_PCI_DEVICE(i2c_designware, designware_pci_supported);
 603 #endif
 604
 605 #endif /* CONFIG_DM_I2C */