git.sur5r.net Git - u-boot/blob - drivers/i2c/i2c-cdns.c

   1 /*
   2  * Copyright (C) 2015 Moritz Fischer <moritz.fischer@ettus.com>
   3  * IP from Cadence (ID T-CS-PE-0007-100, Version R1p10f2)
   4  *
   5  * This file is based on: drivers/i2c/zynq_i2c.c,
   6  * with added driver-model support and code cleanup.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #include <common.h>
  12 #include <linux/types.h>
  13 #include <linux/io.h>
  14 #include <asm/errno.h>
  15 #include <dm/device.h>
  16 #include <dm/root.h>
  17 #include <i2c.h>
  18 #include <fdtdec.h>
  19 #include <mapmem.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 /* i2c register set */
  24 struct cdns_i2c_regs {
  25         u32 control;
  26         u32 status;
  27         u32 address;
  28         u32 data;
  29         u32 interrupt_status;
  30         u32 transfer_size;
  31         u32 slave_mon_pause;
  32         u32 time_out;
  33         u32 interrupt_mask;
  34         u32 interrupt_enable;
  35         u32 interrupt_disable;
  36 };
  37
  38 /* Control register fields */
  39 #define CDNS_I2C_CONTROL_RW             0x00000001
  40 #define CDNS_I2C_CONTROL_MS             0x00000002
  41 #define CDNS_I2C_CONTROL_NEA            0x00000004
  42 #define CDNS_I2C_CONTROL_ACKEN          0x00000008
  43 #define CDNS_I2C_CONTROL_HOLD           0x00000010
  44 #define CDNS_I2C_CONTROL_SLVMON         0x00000020
  45 #define CDNS_I2C_CONTROL_CLR_FIFO       0x00000040
  46 #define CDNS_I2C_CONTROL_DIV_B_SHIFT    8
  47 #define CDNS_I2C_CONTROL_DIV_B_MASK     0x00003F00
  48 #define CDNS_I2C_CONTROL_DIV_A_SHIFT    14
  49 #define CDNS_I2C_CONTROL_DIV_A_MASK     0x0000C000
  50
  51 /* Status register values */
  52 #define CDNS_I2C_STATUS_RXDV    0x00000020
  53 #define CDNS_I2C_STATUS_TXDV    0x00000040
  54 #define CDNS_I2C_STATUS_RXOVF   0x00000080
  55 #define CDNS_I2C_STATUS_BA      0x00000100
  56
  57 /* Interrupt register fields */
  58 #define CDNS_I2C_INTERRUPT_COMP         0x00000001
  59 #define CDNS_I2C_INTERRUPT_DATA         0x00000002
  60 #define CDNS_I2C_INTERRUPT_NACK         0x00000004
  61 #define CDNS_I2C_INTERRUPT_TO           0x00000008
  62 #define CDNS_I2C_INTERRUPT_SLVRDY       0x00000010
  63 #define CDNS_I2C_INTERRUPT_RXOVF        0x00000020
  64 #define CDNS_I2C_INTERRUPT_TXOVF        0x00000040
  65 #define CDNS_I2C_INTERRUPT_RXUNF        0x00000080
  66 #define CDNS_I2C_INTERRUPT_ARBLOST      0x00000200
  67
  68 #define CDNS_I2C_FIFO_DEPTH             16
  69 #define CDNS_I2C_TRANSFER_SIZE_MAX      255 /* Controller transfer limit */
  70
  71 #ifdef DEBUG
  72 static void cdns_i2c_debug_status(struct cdns_i2c_regs *cdns_i2c)
  73 {
  74         int int_status;
  75         int status;
  76         int_status = readl(&cdns_i2c->interrupt_status);
  77
  78         status = readl(&cdns_i2c->status);
  79         if (int_status || status) {
  80                 debug("Status: ");
  81                 if (int_status & CDNS_I2C_INTERRUPT_COMP)
  82                         debug("COMP ");
  83                 if (int_status & CDNS_I2C_INTERRUPT_DATA)
  84                         debug("DATA ");
  85                 if (int_status & CDNS_I2C_INTERRUPT_NACK)
  86                         debug("NACK ");
  87                 if (int_status & CDNS_I2C_INTERRUPT_TO)
  88                         debug("TO ");
  89                 if (int_status & CDNS_I2C_INTERRUPT_SLVRDY)
  90                         debug("SLVRDY ");
  91                 if (int_status & CDNS_I2C_INTERRUPT_RXOVF)
  92                         debug("RXOVF ");
  93                 if (int_status & CDNS_I2C_INTERRUPT_TXOVF)
  94                         debug("TXOVF ");
  95                 if (int_status & CDNS_I2C_INTERRUPT_RXUNF)
  96                         debug("RXUNF ");
  97                 if (int_status & CDNS_I2C_INTERRUPT_ARBLOST)
  98                         debug("ARBLOST ");
  99                 if (status & CDNS_I2C_STATUS_RXDV)
 100                         debug("RXDV ");
 101                 if (status & CDNS_I2C_STATUS_TXDV)
 102                         debug("TXDV ");
 103                 if (status & CDNS_I2C_STATUS_RXOVF)
 104                         debug("RXOVF ");
 105                 if (status & CDNS_I2C_STATUS_BA)
 106                         debug("BA ");
 107                 debug("TS%d ", readl(&cdns_i2c->transfer_size));
 108                 debug("\n");
 109         }
 110 }
 111 #endif
 112
 113 struct i2c_cdns_bus {
 114         int id;
 115         struct cdns_i2c_regs __iomem *regs;     /* register base */
 116 };
 117
 118 /* Wait for an interrupt */
 119 static u32 cdns_i2c_wait(struct cdns_i2c_regs *cdns_i2c, u32 mask)
 120 {
 121         int timeout, int_status;
 122
 123         for (timeout = 0; timeout < 100; timeout++) {
 124                 udelay(100);
 125                 int_status = readl(&cdns_i2c->interrupt_status);
 126                 if (int_status & mask)
 127                         break;
 128         }
 129
 130         /* Clear interrupt status flags */
 131         writel(int_status & mask, &cdns_i2c->interrupt_status);
 132
 133         return int_status & mask;
 134 }
 135
 136 static int cdns_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
 137 {
 138         struct i2c_cdns_bus *bus = dev_get_priv(dev);
 139
 140         if (speed != 100000) {
 141                 printf("%s, failed to set clock speed to %u\n", __func__,
 142                        speed);
 143                 return -EINVAL;
 144         }
 145
 146         /* TODO: Calculate dividers based on CPU_CLK_1X */
 147         /* 111MHz / ( (3 * 17) * 22 ) = ~100KHz */
 148         writel((16 << CDNS_I2C_CONTROL_DIV_B_SHIFT) |
 149                 (2 << CDNS_I2C_CONTROL_DIV_A_SHIFT), &bus->regs->control);
 150
 151         /* Enable master mode, ack, and 7-bit addressing */
 152         setbits_le32(&bus->regs->control, CDNS_I2C_CONTROL_MS |
 153                 CDNS_I2C_CONTROL_ACKEN | CDNS_I2C_CONTROL_NEA);
 154
 155         return 0;
 156 }
 157
 158 /* Probe to see if a chip is present. */
 159 static int cdns_i2c_probe_chip(struct udevice *bus, uint chip_addr,
 160                                 uint chip_flags)
 161 {
 162         struct i2c_cdns_bus *i2c_bus = dev_get_priv(bus);
 163         struct cdns_i2c_regs *regs = i2c_bus->regs;
 164
 165         /* Attempt to read a byte */
 166         setbits_le32(&regs->control, CDNS_I2C_CONTROL_CLR_FIFO |
 167                 CDNS_I2C_CONTROL_RW);
 168         clrbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
 169         writel(0xFF, &regs->interrupt_status);
 170         writel(chip_addr, &regs->address);
 171         writel(1, &regs->transfer_size);
 172
 173         return (cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
 174                 CDNS_I2C_INTERRUPT_NACK) &
 175                 CDNS_I2C_INTERRUPT_COMP) ? 0 : -ETIMEDOUT;
 176 }
 177
 178 static int cdns_i2c_write_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
 179                                u32 len, bool next_is_read)
 180 {
 181         u8 *cur_data = data;
 182
 183         struct cdns_i2c_regs *regs = i2c_bus->regs;
 184
 185         setbits_le32(&regs->control, CDNS_I2C_CONTROL_CLR_FIFO |
 186                 CDNS_I2C_CONTROL_HOLD);
 187
 188         /* if next is a read, we need to clear HOLD, doesn't work */
 189         if (next_is_read)
 190                 clrbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
 191
 192         clrbits_le32(&regs->control, CDNS_I2C_CONTROL_RW);
 193
 194         writel(0xFF, &regs->interrupt_status);
 195         writel(addr, &regs->address);
 196
 197         while (len--) {
 198                 writel(*(cur_data++), &regs->data);
 199                 if (readl(&regs->transfer_size) == CDNS_I2C_FIFO_DEPTH) {
 200                         if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP)) {
 201                                 /* Release the bus */
 202                                 clrbits_le32(&regs->control,
 203                                              CDNS_I2C_CONTROL_HOLD);
 204                                 return -ETIMEDOUT;
 205                         }
 206                 }
 207         }
 208
 209         /* All done... release the bus */
 210         clrbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
 211         /* Wait for the address and data to be sent */
 212         if (!cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP))
 213                 return -ETIMEDOUT;
 214         return 0;
 215 }
 216
 217 static int cdns_i2c_read_data(struct i2c_cdns_bus *i2c_bus, u32 addr, u8 *data,
 218                               u32 len)
 219 {
 220         u32 status;
 221         u32 i = 0;
 222         u8 *cur_data = data;
 223
 224         /* TODO: Fix this */
 225         struct cdns_i2c_regs *regs = i2c_bus->regs;
 226
 227         /* Check the hardware can handle the requested bytes */
 228         if ((len < 0) || (len > CDNS_I2C_TRANSFER_SIZE_MAX))
 229                 return -EINVAL;
 230
 231         setbits_le32(&regs->control, CDNS_I2C_CONTROL_CLR_FIFO |
 232                 CDNS_I2C_CONTROL_RW);
 233
 234         /* Start reading data */
 235         writel(addr, &regs->address);
 236         writel(len, &regs->transfer_size);
 237
 238         /* Wait for data */
 239         do {
 240                 status = cdns_i2c_wait(regs, CDNS_I2C_INTERRUPT_COMP |
 241                         CDNS_I2C_INTERRUPT_DATA);
 242                 if (!status) {
 243                         /* Release the bus */
 244                         clrbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
 245                         return -ETIMEDOUT;
 246                 }
 247                 debug("Read %d bytes\n",
 248                       len - readl(&regs->transfer_size));
 249                 for (; i < len - readl(&regs->transfer_size); i++)
 250                         *(cur_data++) = readl(&regs->data);
 251         } while (readl(&regs->transfer_size) != 0);
 252         /* All done... release the bus */
 253         clrbits_le32(&regs->control, CDNS_I2C_CONTROL_HOLD);
 254
 255 #ifdef DEBUG
 256         cdns_i2c_debug_status(regs);
 257 #endif
 258         return 0;
 259 }
 260
 261 static int cdns_i2c_xfer(struct udevice *dev, struct i2c_msg *msg,
 262                          int nmsgs)
 263 {
 264         struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
 265         int ret;
 266
 267         debug("i2c_xfer: %d messages\n", nmsgs);
 268         for (; nmsgs > 0; nmsgs--, msg++) {
 269                 bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD);
 270
 271                 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
 272                 if (msg->flags & I2C_M_RD) {
 273                         ret = cdns_i2c_read_data(i2c_bus, msg->addr, msg->buf,
 274                                                  msg->len);
 275                 } else {
 276                         ret = cdns_i2c_write_data(i2c_bus, msg->addr, msg->buf,
 277                                                   msg->len, next_is_read);
 278                 }
 279                 if (ret) {
 280                         debug("i2c_write: error sending\n");
 281                         return -EREMOTEIO;
 282                 }
 283         }
 284
 285         return 0;
 286 }
 287
 288 static int cdns_i2c_ofdata_to_platdata(struct udevice *dev)
 289 {
 290         struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev);
 291
 292         i2c_bus->regs = (struct cdns_i2c_regs *)dev_get_addr(dev);
 293         if (!i2c_bus->regs)
 294                 return -ENOMEM;
 295
 296         return 0;
 297 }
 298
 299 static const struct dm_i2c_ops cdns_i2c_ops = {
 300         .xfer = cdns_i2c_xfer,
 301         .probe_chip = cdns_i2c_probe_chip,
 302         .set_bus_speed = cdns_i2c_set_bus_speed,
 303 };
 304
 305 static const struct udevice_id cdns_i2c_of_match[] = {
 306         { .compatible = "cdns,i2c-r1p10" },
 307         { /* end of table */ }
 308 };
 309
 310 U_BOOT_DRIVER(cdns_i2c) = {
 311         .name = "i2c-cdns",
 312         .id = UCLASS_I2C,
 313         .of_match = cdns_i2c_of_match,
 314         .ofdata_to_platdata = cdns_i2c_ofdata_to_platdata,
 315         .priv_auto_alloc_size = sizeof(struct i2c_cdns_bus),
 316         .ops = &cdns_i2c_ops,
 317 };